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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉換器參考手冊 |
| 文件頁數(shù)： | 63/122頁 |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
DIGITAL CONTROL
MOTOROLA
7-17
SSE1 — Queue 1 Single-Scan Enable Bit
SSE1 enables a single-scan of queue 1 to start after a trigger event occurs. The SSE1
bit may be set to a one during the same write cycle when the MQ1 bits are set for one
of the single-scan queue operating modes. The single-scan enable bit can be written
as a one or a zero, but is always read as a zero, unless a test mode is selected. The
SSE1 bit enables a trigger event to initiate queue execution for any single-scan oper-
ation on queue 1. The QADC clears the SSE1 bit when the single-scan is complete.
0 = Trigger events are not accepted for single-scan modes.
1 = Accept a trigger event to start queue 1 in a single-scan mode.
MQ1[10:8] — Queue 1 Operating Mode
The MQ1 field selects the queue operating mode for queue 1.
Table 7-4
shows the bits in the MQ1 field which enable different queue 1 operating
modes.
7.6.3 Control Register 2
Control register 2 is the mode control register for the operation of queue 2. Software
specifies the queue operating mode of queue 2, and may enable a completion and/or
a pause interrupt. All control register fields are read/write data, except the SSE2 bit,
which is readable only when the test mode is enabled. Most of the bits are typically
written once when the software initializes the QADC, and not changed afterwards.
CIE2 — Queue 2 Completion Software Interrupt Enable
CIE2 enables an interrupt upon completion of queue 2. The interrupt request is initiat-
ed when the conversion is complete for the CCW in queue 2.
0 = Disable the queue completion interrupt associated with queue 2.
1 = Enable an interrupt after the conversion of the sample requested by the last
CCW in queue 2.
Table 7-4 Queue 1 Operating Modes
MQ1[10:8]
000
001
010
011
100
101
110
111
Operating Modes
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE1)
External trigger rising edge single-scan mode (on ETRIG1 pin)
External trigger falling edge single-scan mode (on ETRIG1 pin)
Reserved mode, conversions do not occur
Continuous-scan software triggered mode
External trigger rising edge continuous-scan mode (on ETRIG1 pin)
External trigger falling edge continuous-scan mode (on ETRIG1 pin)
QACR2 —
Control Register 2
$####0E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIE2
PIE2
SSE2
MQ2
RES
NOT
USED
BQ2
RESET:
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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