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參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁數(shù)： | 76/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
7-30
DIGITAL CONTROL
QADC
REFERENCE MANUAL
BYP — Sample Amplifier Bypass
Setting the BYP field in the CCW enables the amplifier bypass mode for a conversion,
and subsequently changes the timing. The initial sample time and the transfer time are
eliminated, reducing the potential conversion time by six QCLKs. However, due to in-
ternal RC effects, a minimum final sample time of four QCLKs must be allowed. This
results in a shortened conversion time of four QCLKS. When using this mode, the ex-
ternal circuit should be of low source impedance. Loading effects of the external cir-
cuitry need to be considered, since the benefits of the sample amplifier are not
present.
0 = Amplifier bypass mode disabled.
1 = Amplifier bypass mode enabled.
IST[7:6] — Input Sample Time
The IST field allows software to specify the length of the sample window. Provision is
made to vary the input sample time, through software control, to offer flexibility in the
source impedance of the circuitry providing the QADC analog channel inputs. Longer
sample times permit more accurate A/D conversions of signals with higher source im-
pedances.
Table 7-7
shows the four selectable input sample times.
Table 7-7 Input Sample Times
The programmable sample time can also be used to increase the time interval be-
tween conversions to adjust the queue execution time or the sampling rate.
In addition to the four sample times listed in
Table 7-7
, the sample amplifier may be
bypassed entirely. This results in a shorter conversion time (by four QCLKs) may also
reduce the effects of the sample amplifier on the system performance. The sample
amplifier can be bypassed on each conversion by setting the BYP bit field in the CCW.
This mode is mainly intended for factory testing, but may also be used in applications
with some considerations.
The bypass option shortens the conversion time by six QCLKs. However, due to inter-
nal RC effects, a minimum final sample time of four QCLKS must be used. This results
in a conversion time savings of four QCLKS. The slightly shorter sample time may be
of use in some applications, depending on system constraints, but may be offset by
the loss of the sample amplifier benefits. This means that external circuit loading from
the QADC may increase due to the direct connection of the internal RC DAC array dur-
ing the sample phase. Typically, the bypass mode may only be used if external source
impedance is kept low. Refer to
APPENDIX A ELECTRICAL CHARACTERISTICS
for information on the maximum allowable input source impedance.
IST[7:6]
00
01
10
11
Input Sample Times
Input sample time = QCLK period x 2
Input sample time = QCLK period x 4
Input sample time = QCLK period x 8
Input sample time = QCLK period x 16
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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