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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊 |
| 文件頁數(shù)： | 68/122頁 |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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MOTOROLA
7-22
DIGITAL CONTROL
QADC
REFERENCE MANUAL
CF2 — Queue 2 Completion Flag
CF2 indicates that a queue 2 scan has been completed. CF2 is set by the QADC when
the input channel sample requested by the last CCW in queue 2 is converted, and the
result is stored in the result table.
The end of queue 2 is identified when the current CCW contains an end-of-queue code
instead of a valid channel number, or when the currently completed CCW is in the last
location of the CCW RAM.
When CF2 is set and interrupts are enabled for that queue completion flag, the QADC
asserts an interrupt request at the level specified by IRL2 in the interrupt register
(QADCINT). The software reads CF2 during an interrupt service routine to identify the
interrupt request. The interrupt request is cleared when the software writes a zero to
the CF2 bit, when the bit was previously read as a one. Once set, only software or re-
set can clear CF2.
CF2 is maintained by the QADC regardless of whether the corresponding interrupts
are enabled. The software polls for CF2 to see if it is set. This allows the software to
recognize that the QADC is finished with a queue 2 scan. The software acknowledges
that it has detected the completion flag being set by writing a zero to the completion
flag after the bit was read as a one.
Refer to
SECTION 8 INTERRUPTS
for more information.
0 = Queue 2 scan is not complete.
1 = Queue 2 scan is complete.
PF2 — Queue 2 Pause Flag
PF2 indicates that a queue 2 scan has reached a pause. PF2 is set by the QADC when
the current queue 2 CCW has the pause bit set, the selected input channel has been
converted, and the result has been stored in the result table.
Once PF2 is set, the queue enters the paused state and waits for a trigger event to
allow queue execution to continue. However, if the CCW with the pause bit set is the
last CCW in a queue, the queue execution is complete. The queue status becomes
idle, not paused, and both the pause and completion flags are set.
When PF2 is set and interrupts are enabled for the corresponding queue, the QADC
asserts an interrupt request at the level specified by IRL2 in the interrupt register. The
software reads PF2 during an interrupt service routine to identify the interrupt request.
The interrupt request is cleared when the software writes a zero to PF2, when the bit
was previously read as a one. Once set, only software or reset can clear PF2.
PF2 is maintained by the QADC regardless of whether the corresponding interrupts
are enabled. The software may poll PF2 to find out when the QADC has reached a
pause in scanning a queue. The software acknowledges that it has detected a pause
flag being set by writing a zero to PF2 after the bit was last read as a one.
0 = Queue 2 has not reached a pause.
1 = Queue 2 has reached a pause.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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