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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 56/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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MOTOROLA
7-10
DIGITAL CONTROL
QADC
REFERENCE MANUAL
terval timer. To retain the specified analog conversion accuracy, the QCLK frequency
(F
QCLK
) must be within the tolerance specified in
APPENDIX A ELECTRICAL CHAR-
ACTERISTICS
.
Before using the QADC, the software must initialize the prescaler with values that put
the QCLK within the specified range. Though most software applications initialize the
prescaler once and do not change it, write operations to the prescaler fields are per-
mitted.
CAUTION
A change in the prescaler value while a conversion is in progress is
likely to corrupt the result from any conversion in progress. There-
fore, any prescaler write operation should be done only when both
queues are in the disabled modes.
Figure 7-2 QADC Clock Subsystem Functions
QADC CLOCK BLOCK
PRESCALER RATE SELECTION
(FROM CONTROL REGISTER 0):
BINARY COUNTER
PERIODIC/INTERVAL
TIMER SELECT
215
214
213
212
211
210
29
28
27
216217
ONE'S COMPLEMENT
COMPARE
CLOCK
GENERATE
5-BIT
DOWN COUNTER
ZERO
DETECT
RESET QCLK
LOAD PSH
SET QCLK
QCLK
QADC CLOCK
(
÷
2 TO
÷
40 )
LOW TIME CYCLES (PSL)
ADD HALF CYCLE TO HIGH (PSA)
HIGH TIME CYCLES (PSH)
INPUT SAMPLE TIME (FROM CCW)
QUEUE 2 MODE RATE SELECTION
(FROM CONTROL REGISTER 2):
SAR CONTROL
SAR[9:0]
PERIODIC/INTERVAL
TRIGGER EVENT
5
3
3
3
1
5
4
SYSTEM CLOCK (FSYS)
A/D CONVERTER
STATE MACHINE
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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