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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 82/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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MOTOROLA
8-2
INTERRUPTS
QADC
REFERENCE MANUAL
If interrupts are enabled for an event, the QADC requests interrupt service when the
event occurs. Using interrupts does not require continuously polling the status flags to
see if an event has taken place. However, status flags must be cleared after an inter-
rupt is serviced, in order to disable the interrupt request.
In both polled and interrupt-driven operating modes, status flags must be re-enabled
after an event occurs. Flags are re-enabled by clearing appropriate QASR bits in a par-
ticular sequence. The register must first be read, then zeros must be written to the
flags that are to be cleared. If a new event occurs between the time that the register is
read and the time that it is written, the associated flag is not cleared.
8.3 Interrupt Sources
The QADC includes four sources of interrupt service requests, each of which is sepa-
rately enabled. Each time the result is written for the last conversion command word
(CCW) in a queue, the completion flag for the corresponding queue is set, and when
enabled, an interrupt request is generated. In the same way, each time the result is
written for a CCW with the pause bit set, the queue pause flag is set, and when en-
abled, an interrupt request is generated. Refer to
Table 8-1
.
The pause and complete interrupts for queue 1 and queue 2 have separate interrupt
vector numbers, so that each source can be separately serviced.
8.4 QADC Interrupt Register
QADCINT specifies the priority level of QADC interrupt requests and the vector pro-
vided during an interrupt acknowledge cycle. The interrupt level for queue 1 and queue
2 may be different. The interrupt register is read/write accessible in supervisor data
space only. The implemented interrupt register fields can be read and written, re-
served locations read zero and writes have no effect. They are typically written once
when the software initializes the QADC, and not changed afterwards.
Table 8-1 QADC Status Flags and Interrupt Sources
Queue
Queue
Activity
Status Flag
Interrupt Enable Bit
Queue 1
Result written to last
CCW in Queue 1
Result written for a
CCW with pause bit
set in Queue 1
Result written to last
CCW in Queue 2
Result written for a
CCW with pause bit
set in Queue 2
CF1
CF1
PF1
PF1
Queue 2
CF2
CF2
PF2
PF2
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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