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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 29/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
EXTERNAL MULTIPLEXING
MOTOROLA
4-1
SECTION 4 EXTERNAL MULTIPLEXING
External multiplexer chips concentrate a number of analog signals onto a few inputs
to the analog converter. This is helpful in applications that need to convert more analog
signals than the A/D converter can normally provide. External multiplexing also puts
the multiplex chip closer to the signal source. This minimizes the number of analog sig-
nals that need to be shielded due to the close proximity to noisy high speed digital sig-
nals at the microcontroller chip.
For example, four 8-input multiplexer chips can be put at the connector where the an-
alog signals first arrive on the computer board. As a result, only four analog signals
need to be shielded from noise as they approach the microcontroller chip, rather than
having to protect 32 analog signals. However, external multiplexer chips may intro-
duce additional noise and errors if not properly utilized. Therefore, it is necessary to
maintain low “on” resistance (the impedance of an analog switch when active within a
multiplex chip) and insert a low pass filter (R/C) on the input side of the multiplex chip.
4.1 External Multiplexing Operation
The QADC can use from one to four external multiplexer chips to expand the number
of analog signals that may be converted. Up to 32 analog channels can be converted
through external multiplexer selection. The externally multiplexed channels are auto-
matically selected from the channel field of the conversion command word (CCW) ta-
ble, the same as internally multiplexed channels. Refer to paragraph 7.7 in
SECTION
7 DIGITAL CONTROL
for additional information on channel number assignments.
All of the automatic queue features are available for externally and internally multi-
plexed channels. The software selects the external multiplexed mode by setting the
MUX bit in control register 0 (QACR0).
Figure 4-1
shows the maximum configuration of four external multiplexer chips con-
nected to the QADC. The external multiplexer chips select one of eight analog inputs
and connect it to one analog output, which becomes an input to the QADC. The QADC
provides three multiplexed address signals — MA0, MA1, and MA2, to select one of
eight inputs. These inputs are connected to all four external multiplexer chips. The an-
alog output of the four multiplex chips are each connected to four separate QADC in-
puts — AN
w
, AN
x
, AN
y
, and AN
z
.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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