參數(shù)資料
型號: QADCRM
英文描述: Queued Analog-to-Digital Converter Reference Manual
中文描述: 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊
文件頁數(shù): 92/122頁
文件大小: 940K
代理商: QADCRM
MOTOROLA
9-6
QUEUE PRIORITY EXAMPLES
QADC
REFERENCE MANUAL
Situations S8 and S9 (
Figure 9-8
and
Figure 9-9
) repeat the same two situations with
the resume bit set to a one. When the RES bit is set, following suspension, queue 2
resumes execution with the aborted CCW, not the first CCW in the queue.
Figure 9-8 CCW Priority Situation 8
Figure 9-9 CCW Priority Situation 9
Situations S10 and S11 (
Figure 9-10
and
Figure 9-11
) show that when an additional
trigger event is detected for queue 2 while the queue is suspended, the trigger overrun
error bit is set, the same as if queue 2 were being executed when a new trigger event
occurs. Trigger overrun on queue 2 thus permits the software to know that queue 1 is
taking up so much QADC time that queue 2 trigger events are being lost.
QADC S8
IDLE
Q1
Q2
QS
IDLE
IDLE
0000
1000
0010
ACTIVE
C1
C2
T1
Q1:
C1
C3
C4
IDLE
Q2:
PF1
PAUSE
ACTIVE
CF1
T1
ACTIVE
SUSPEND
0100
ACTIVE
0110
1010
C2
C3
C4
CF2
T2
0000
QADC S9
T1
PAUSE
Q1
Q2
QS
IDLE
ACTIVE
IDLE
ACT
IDLE
0010
0110
1010
0010
ACTIVE
0000
IDLE
Q1:
PF1
C1
C2
0000
1010
0101
ACTIVE
PAUSE
0110
C1
Q2:
T2
C2
PF2
T1
C3
C4
CF1
C4
CF2
SUSPEND
ACT
ACTIVE
SUSPEND
T2
C3
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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