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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁數(shù)： | 23/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
CONFIGURATION AND CONTROL
MOTOROLA
3-3
Word accesses to an odd address require two bus cycles; half of two different 16-bit
QADC locations are accessed. The first bus cycle is treated by the QADC as an 8-bit
read or write of an odd address. The second cycle is an 8-bit read or write of an even
address. The QADC address space is organized into 16-bit even address locations,
so a 16-bit read or write of an odd address obtains or provides the lower half of one
QADC location, and the upper half of the following QADC location.
Long word (32-bit) accesses to an even address require two bus cycles to complete
the access, and two full QADC locations are accessed. The first bus cycle reads or
writes the addressed 16-bit QADC location and the second cycle reads or writes the
following 16-bit location.
Long word accesses to an odd address require three bus cycles. Portions of three dif-
ferent QADC locations are accessed. The first bus cycle is treated by the QADC as an
8-bit access of an odd address, the second cycle is a 16-bit aligned access, and the
third cycle is an 8-bit access of an even address. The QADC address space is orga-
nized into 16-bit even address locations, so a 32-bit read or write of an odd address
provides the lower half of one QADC location, the full 16-bit content of the following
QADC location, and the upper half of the third QADC location.
3.3 Module Configuration
The module configuration register (QADCMCR) contains parameters which allow the
QADC to interface with other MCU modules. The register defines freeze and stop
mode operation, supervisor-only access protection, and the QADC software interrupt
arbitration priority number. The implemented fields can be read and written. Unimple-
mented locations read zero and writes have no effect. They are typically written once
when the software initializes the QADC, and not changed afterwards.
3.3.1 Low Power Stop Mode
When the STOP bit in the QADCMCR is set, the clock signal to the A/D converter is
disabled, effectively turning off the analog circuitry. This results in a static, low power
consumption, idle condition. The stop mode aborts any conversion sequence in
progress. Because the bias currents to the analog circuits are turned off in stop mode,
the QADC requires some recovery time (T
SR
in
APPENDIX A ELECTRICAL CHAR-
ACTERISTICS
) to stabilize the analog circuits after the stop enable bit is cleared.
In the stop mode, the BIU state machine and logic do not shut down, and the QADC-
MCR, the interrupt register (QADCINT), and the test register (QADCTEST) are fully
accessible and are not reset. The data direction register (DDRQA), port data register
(PORTQA/PORTQB), and control register 0 (QACR0) are not reset and are read-only
accessible. The RAM is not reset and is not accessible. Control register 1 (QACR1),
control register 2 (QACR2), and the status register (QASR) are reset and are read-only
accessible. In addition, the QADC clock (QCLK) and the periodic/interval timer are
held in reset during stop mode.
If the STOP bit is clear, stop mode is disabled.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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