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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊 |
| 文件頁數(shù)： | 60/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
7-14
DIGITAL CONTROL
QADC
REFERENCE MANUAL
is selected, the timer counter is reset after the current conversion completes. When
the periodic or interval timer mode has been enabled (the timer is counting), but a trig-
ger event has not been issued, the freeze mode takes effect immediately, and the tim-
er is held in reset. When the internal FREEZE line is negated, the timer counter starts
counting from the beginning. Refer to paragraph 3.3.2 in
SECTION 3 CONFIGURA-
TION AND CONTROL
for more information.
7.6 Control and Status Registers
The following paragraphs describe the control and status registers. The QADC has
three control registers and one status register.
7.6.1 Control Register 0
Control register 0 establishes the QCLK with prescaler parameter fields and defines
whether external multiplexing is enabled. All of the implemented control register fields
can be read or written, reserved locations read zero and writes have no effect. They
are typically written once when the software initializes the QADC, and not changed af-
terwards.
MUX — Externally Multiplexed Mode
The MUX bit allows the software to select the externally multiplexed mode, which af-
fects the interpretation of the channel numbers and forces the MA0, MA1 and MA2
pins to be outputs.
0 = Internally multiplexed, 16 possible channels.
1 = Externally multiplexed, 44 possible channels.
PSH[8:4] — Prescaler Clock High Time
The PSH field selects the QCLK high time in the prescaler. Refer to
APPENDIX A
ELECTRICAL CHARACTERISTICS
for information on QADC operating clock fre-
quency (F
) values. To keep the QCLK within the specified range, the PSH field se-
lects the high time of the QCLK, which can range from 1 to 32 system clock cycles.
The minimum high time for the QCLK is specified as T
PSH
.
Table 7-2
displays the bits in PSH field which enable a range of QCLK high times.
QACR0 —
Control Register 0
$####0A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MUX
RESERVED
PSH
PSA
PSL
RESET:
0
0
0
0
1
1
0
0
1
1
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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