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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉換器參考手冊 |
| 文件頁數(shù)： | 51/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
DIGITAL CONTROL
MOTOROLA
7-5
Until the single-scan enable bit is set, any trigger events for that queue are ignored.
The single-scan enable bit may be set to a one during the write cycle, which selects
the single-scan queue operating mode. The single-scan enable bit can be written as a
one or a zero, but is always read as a zero. The completion flag, completion interrupt,
or queue status are used to determine when the queue has completed.
After the single-scan enable bit is set, a trigger event causes the QADC to begin exe-
cution with the first CCW in the queue. The single-scan enable bit remains set until the
queue is completed. After the queue reaches completion, the QADC resets the single-
scan enable bit to zero. If the single-scan enable bit is written to a one or a zero by the
software before the queue scan is complete, the queue is not affected. However, if the
software changes the queue operating mode, the new queue operating mode and the
value of the single-scan enable bit are recognized immediately. The current conver-
sion is aborted and the new queue operating mode takes effect.
In the software initiated single-scan mode, the writing of a one to the single-scan en-
able bit causes the QADC to internally generate a trigger event and the queue execu-
tion begins immediately. In the other single-scan queue operating modes, once the
single-scan enable bit is written, the selected trigger event must occur before the
queue can start. A trigger overrun is recorded if a trigger event occurs during queue
execution in the external trigger single-scan mode and the interval timer single-scan
mode.
When a pause bit is encountered during the queue scan in a single-scan mode, anoth-
er trigger event is required for queue execution to continue. Software involvement is
not needed to enable queue execution to continue from the paused state. The single-
scan enable bit allows the entire queue to be scanned once.
In the software initiated single-scan mode, the trigger event is generated internally as
soon as the conversion is complete for the CCW with the pause bit set. The pause is
two QCLKs. In the external trigger single-scan mode, the queue remains paused until
another trigger edge is received on the external trigger pin.
In the interval timer single-scan mode, the next expiration of the timer is the trigger
event for the queue. After the queue execution is complete, the queue status is shown
as idle. The software can restart the queue by setting the single-scan enable bit to a
one. Queue execution begins with the first CCW in the queue.
7.3.2.1 Software Initiated Single-Scan Mode
Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting
the software initiated single-scan mode, and writing the single-scan enable bit in
QACR1 or QACR2. A trigger event is generated internally and the QADC immediately
begins execution of the first CCW in the queue. If a pause is encountered, queue ex-
ecution ceases momentarily while another trigger event is generated internally, and
then execution continues.
The QADC automatically performs the conversions in the queue until an end-of-queue
condition is encountered. The queue remains idle until the software again sets the sin-
gle-scan enable bit. While the time to internally generate and act on a trigger event is
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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