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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 104/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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MOTOROLA
B-4
REGISTER SUMMARY
QADC
REFERENCE MANUAL
Since port B is input-only, a data direction register is not needed. Therefore, the lower
byte of the port data direction register is not implemented. Read operations on the re-
served bits return zeros, and writes have no effect.
B.2.6 QADC Control Registers
MUX — Externally Multiplexed Mode
The MUX bit allows the software to select the externally multiplexed mode, which af-
fects the interpretation of the channel numbers and forces the MA0, MA1 and MA2
pins to be outputs.
0 = Internally multiplexed, 16 possible channels.
1 = Externally multiplexed, 44 possible channels.
PSH[8:4] — Prescaler Clock High Time
The PSH field selects the QADC clock (QCLK) high time in the prescaler.
Table B-2
displays the bits in PSH field which enable a range of QCLK high times.
PSA — Prescaler Add a Clock Tic
0 = QCLK high and low times are not modified.
1 = Add one system clock half cycle to the high time of the QCLK and subtract one
system clock half cycle from the low time.
PSL[2:0] — Prescaler Clock Low Time
The PSL field selects the QADC clock (QCLK) low time in the prescaler.
Table B-2
displays the bits in PSL field which enable a range of QCLK low times.
QACR0 —
Control Register 0
$####0A
15
MUX
RESET:
0
14
13
12
RESERVED
11
10
9
8
7
6
5
4
3
2
1
0
PSH
PSA
PSL
0
0
0
1
1
0
0
1
1
Table B-2 Prescaler Clock High Times
PSH[8:4]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
QCLK High Time
1 System Clock Cycle
2 System Clock Cycles
3 System Clock Cycles
4 System Clock Cycles
5 System Clock Cycles
6 System Clock Cycles
7 System Clock Cycles
8 System Clock Cycles
9 System Clock Cycles
10 System Clock Cycles
11 System Clock Cycles
12 System Clock Cycles
13 System Clock Cycles
14 System Clock Cycles
15 System Clock Cycles
16 System Clock Cycles
PSH[8:4]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
QCLK High Time
17 System Clock Cycles
18 System Clock Cycles
19 System Clock Cycles
20 System Clock Cycles
21 System Clock Cycles
22 System Clock Cycles
23 System Clock Cycles
24 System Clock Cycles
25 System Clock Cycles
26 System Clock Cycles
27 System Clock Cycles
28 System Clock Cycles
29 System Clock Cycles
30 System Clock Cycles
31 System Clock Cycles
32 System Clock Cycles
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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