參數(shù)資料
型號： T8102A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時隙Interchangers
文件頁數(shù)： 108/112頁
文件大?。?/td> 1408K
代理商： T8102A
104
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
Appendix B. Minimum Delay and
Constant Delay Connections
(continued)
B.2 Delay Type Definitions
Constant Delay This is a well-defined, predictable, and
linear region of latency in which the
to
time slot is at least 128 time slots after
the
from
time slot, but no more than
256 time slots after the
from
time slot.
Mathematically, constant delay latency is described as
follows*, with L denoting latency, and FME set to the
value indicated:
Forward Connections, FME = 1: L = 128 + TS
(0
≤
TS
≤
127)
Reverse Connections, FME = 0: L = 256 + TS
(–127
≤
TS
≤
0)
* Since TS
= TS(to) – TS(from), the user can modify the equations
to solve for either TS(to) or TS(from).
Minimum Delay This is the most common type of
switching, but has a shorter range than
constant delay, and the user must be
aware of exceptions caused by interac-
tions between the device's internal
pipeline and the dual buffering. The
to
time slot is at least three time slots
after the
from
time slot, but no more
than 128 time slots after the
from
time
slot. Exceptions exist at TS
s of +1,
+2, –126, and –127.
Forward Connections, FME = 0: L = TS
(3
≤
TS
≤
127)
Reverse Connections, FME = 1: L = 128 + TS
(–125
≤
TS
≤
0)
Example:
Switching from TS(37) to TS(1) as a con-
stant delay, the delta is –36, so FME is
set to 0 and the resulting latency is 256 –
36 = 220 time slots. Thus, the connec-
tion will be made from TS(37) of
Frame(n) to TS(1) of Frame(n + 2).
Simple
Summary:
Use constant delay for latencies of 128
to 256 time slots, set FME = 1 for forward
connections, set FME = 0 for reverse
connections.
Example:
Using the same switching from the
example above, TS(37) to TS(1), the
delta is –36, so FME is set to 1 to effect
the minimum delay (setting to 0 effects
constant delay), and the resulting
latency is 128 – 36 = 92 time slots. The
relative positions of the end time slots
are the same in both minimum and con-
stant delay (i.e., they both switch to
TS[1]), but the actual data is delayed by
an additional frame in the constant delay
case.
Simple
Summary:
Use minimum delay for latencies of 3 to
128 time slots, set FME = 0 for forward
connections, set FME = 1 for reverse
connections.
5-6223 (F)
Figure 39. Constant Delay Connections, CON[1:0] = 0X
A
(
RESULTING LATENCY
(TIME SLOTS)
–127
128
0
127
255
256
FME= 0
FME= 1
129
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相關代理商/技術參數(shù)
參數(shù)描述
T810-400B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS
T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
T810-600B 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復通態(tài)電流:120 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:TO-220AB
T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
T810-600B-TR 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復通態(tài)電流:120 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:TO-220AB
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