參數(shù)資料
型號： T8102A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時隙Interchangers
文件頁數(shù)： 55/112頁
文件大小： 1408K
代理商： T8102A
Lucent Technologies Inc.
51
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.5 Clocking Section
(continued)
2.5.8 Clock Control Register Definitions
(continued)
Table 48. CKP: Clocks, Programmable Outputs, 0x02
Clock register 0x02, CKP is the programmed clocks register. It is used for programming the CT_C8 clocks and
enabling its outputs. It is also used to program the TCLK selector. CT_C8 may be operated as either 8 MHz (nor-
mal or inverted) or 4 MHz (normal or inverted). C8IS is used to invert the synchronization on C8A and C8B when
they are selected for input. The C8 and FRAME signals, which are also generated internally, are routed to both the
CT_C8A and /CT_FRAMEA and to the CT_C8B and /CT_FRAMEB. The CAE and CBE pins enable these output
pairs independently. The C8C4 pin selects 8.192 MHz or 4.096 MHz signals to be output on C8A and C8B (for sup-
porting for either ECTF or MC-1 applications). CFW selects the output width of the compatibility frame. The register
format is as follows.
Reg
CKP
R/W
—
Bit 7
Bit 6
PTS
Bit 5
Bit 4
C8IS
Bit 3
CAE
Bit 2
CBE
Bit 1
C8C4
Bit 0
CFW
Symbol
PTS
Bit
7—5 The three PTS bits select the output sent to the TCLK. This output is intended to be used for
driving framers.
PTS = 000,
3-state.
PTS = 001,
Oscillator, buffered output.
PTS = 010,
PLL #2, direct output .
PTS = 011,
PLL #2, output divided by 2.
PTS = 100,
2.048 MHz from state machines.
PTS = 101,
4.096 MHz from state machines.
PTS = 110,
8.192 MHz from state machines.
PTS = 111,
16.384 MHz from state machines.
4
C8IS = 0,
MC-1 (A and B clocks inputs interpreted as /C4 with /FRAME).
C8IS = 1,
ECTF (A and B clocks inputs interpreted as C8 with /FRAME).
3
CAE = 0,
Disable CT_C8A & /CT_FRAMEA outputs.
CAE = 1,
Enable CT_C8A & /CT_FRAMEA outputs. (The devices will auto-
matically disable these on an A clock failure.)
2
CBE = 0,
Disable CT_C8B & /CT_FRAMEB outputs.
CBE = 1,
Enable CT_C8B & /CT_FRAMEB outputs. (The devices will auto-
matically disable these on a B clock failure.)
1
C8C4 = 0,
Inverted 4.096 MHz (MC-1 output mode).
C8C4 = 1,
Noninverted 8.192 MHz (ECTF output mode).
0
CFW = 0,
Narrow (122 ns) /FR_COMP
CFW = 1,
Wide (244 ns) /FR_COMP
Description
C8IS
CAE
CBE
C8C4
CFW
相關(guān)PDF資料
PDF描述
T8105A H.100/H.110 Interface and Time-Slot Interchangers
T8100 H.100/H.110 Interface and Time-Slot Interchanger
T8110 Version History
T8301 T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP
T8302 T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T810-400B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS
T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
T810-600B 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
T810-600B-TR 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*