參數(shù)資料
型號： T8102A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時隙Interchangers
文件頁數(shù)： 78/112頁
文件大?。?/td> 1408K
代理商： T8102A
74
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
3 Using the TSI Devices
(continued)
3.4 Using the LAR, AMR, and IDR for Connections
(continued)
3.4.1 Setting Up Local Connections (T8100A, T8105 Only)
(continued)
Table 70. IDR: Indirect Data Register, Local Connections Only
The second transfer requires that data in the IDR be defined as follows.
After the second transfer is made, the entire 15 bits will be loaded into the connection memory; i.e., the second
transfer triggers the actual memory access. Figure 22 shows how the connections are made from the perspective
of the registers and memory contents.
If the user wishes to set up a pattern mode connection, then the first transfer is a full 8 bits (i.e., the pattern), rather
than the 7-bit time-slot value. This pattern byte will be stored in the lowest 8 bits of the selected connection memory
location. The pattern byte will be sent instead of a byte from local data memory during the output stream and time
slot which corresponds to the connection memory location.
5-6115aF
Figure 22. Local-to-Local Connection Programming (T8100A, T8105 Only)
Reg
IDR
R/W
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control
Address
XCS
PME
FME
CHE
Symbol
XCS
Bit
7
Description
A programmable bit which is routed to the XCS pin one time slot prior to the data to
which it relates.
A high enables the pattern mode; the lower 8 bits of the connection address (time slot
and stream LSB) is routed to the time slot instead of data.
A high enables the use of the alternate data buffer. (Refer to Appendix B for minimum
and constant delay settings.)
Enables the time-slot connection; a low in this bit forces 3-state during the time slot.
All 4 bits are used for the stream address of the desired data memory location.
PME
6
FME
5
CHE
Address
4
3—0
0000 0111
3, 27
3, 28
3, 29
3, 30
3, 31
CONNECTION
MEMORY
0100 0011
0001 1101
0000 0111
AMR
LAR
IDR
WRITE TO
TIME-SLOT
FIELD IN
CONNECTION
MEMORY
FIRST TRANSFER:
0000 0111
0001
1110
3, 27
3, 28
3, 29
3, 30
3, 31
CONNECTION
MEMORY
0101 0011
0001 1101
0001 1110
AMR
LAR
IDR
WRITE TO
FIELD IN
MEMORY
SECOND TRANSFER:
LOCAL MEMORY PROGRAMMING EXAMPLE: CONNECT FROM 14, 7 TO 3, 29 (STREAM, TIME SLOT)
CONNECTION
CONTROL/STREAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T810-400B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS
T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
T810-600B 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
T810-600B-TR 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
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