參數(shù)資料
型號(hào)： T8102A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁數(shù)： 21/112頁
文件大?。?/td> 1408K
代理商： T8102A
Lucent Technologies Inc.
17
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.1 Register/Memory Maps
(continued)
2.1.4 Control Register Memory Space
Function of LAR values when AMR = 0x00. All control registers reset to 0x00. All designations of MSB (most signif-
icant bit) and LSB (least significant bit) are shown.
Table 11. Control Register Memory Space
Register Address
0, 0x00
1, 0x01
2, 0x02
3, 0x03
4, 0x04
5, 0x05
6, 0x06
7, 0x07
8, 0x08
9, 0x09
10—11, 0x0A—0x0B
12, 0x0C
13, 0x0D
14, 0x0E
15, 0x0F
16, 0x10
17, 0x11
18—22, 0x12—0x16
23, 0x17
24, 0x18
25—31, 0x19—0x1F
32, 0x20
33, 0x21
34, 0x22
35, 0x23
36, 0x24
37, 0x25
38—39, 0x26—0x27
40, 0x28
41, 0x29
42, 0x2A
43, 0x2B
44, 0x2C
45—47, 0x2D—0x2F
48, 0x30
49, 0x31
50, 0x32
51—253, 0x33—0xFD
254, 0xFE
255, 0xFF
Register Mnemonic
CKM
CKN
CKP
CKR
CKS
CK32
CK10
CKMD
CKND
CKRD
(Reserved)
LBS
(Reserved)
CON
(Reserved)
HSL
HSH
(Reserved)
GPD
GPR
(Reserved)
FRLA
FRHA
FRLB
FRHB
FRPL
FRPH
(Reserved)
CLKERR1
CLKERR2
SYSERR
CKW
CLKERR3
(Reserved)
DIAG1
DIAG2
DIAG3
(Reserved)
DEV_ID
GMODE
Description
Refer to Section
2.5.8
2.5.8
2.5.8
2.5.8
2.5.8
2.5.8
2.5.8
2.5.8
2.5.8
2.5.8
—
2.2.4
—
Appendix B
—
2.3.5
2.3.5
—
2.6.2
2.6.2
—
2.6.3
2.6.3
2.6.3
2.6.3
2.6.3
2.6.3
—
2.7
2.7
2.7
2.5.7 & 2.7
2.7
—
2.9.2
2.9.2
2.9.2
—
3.2.1
3.2.1
Clocks, Main Clock Selections
Clocks, NETREF Selections
Clocks, Programmable Outputs
Clocks, Resource Selection
Clocks, Secondary (Fallback) Selection
Clocks, Locals 3 and 2
Clocks, Locals 1 and 0
Clocks, Main Divider
Clocks, NETREF Divider
Clocks, Resource Divider
—
Local Stream Control
—
Connection Delay Type
—
H-Bus Stream Control, Low Byte
H-Bus Stream Control, High Byte
—
General-purpose Register, Direction Control
General-purpose I/O Register
—
Frame Group A, Start Address, Low
Frame Group A, High Address and Control
Frame Group B, Start Address, Low
Frame Group B, High Address and Control
Frame Group B, Programmed Output, Low
Frame Group B, Programmed Output, High
—
Clock Error Register, Error Indicator
Clock Error Register, Current Status
System Error Register
Clock Error/Watchdog Masking Register
Clock Error Register, Current Status
—
Diagnostics Register 1
Diagnostics Register 2
Diagnostics Register 3
—
Device Revision Status Register
Global Mode Register
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T810-400B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS
T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
T810-600B 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
T810-600B-TR 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
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