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| 型號： | T8102A |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchangers |
| 中文描述： | H.100/H.110接口和時隙Interchangers |
| 文件頁數(shù)： | 47/112頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | T8102A |
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Lucent Technologies Inc.
43
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Descrip-
tion
(continued)
2.4 Subrate Switching for the Ambassador
Family
(continued)
2.4.6 Minimum vs. Constant Delay
The same issues involved with
virtual framing
exist in
subrate switching as in traditional switching. The sce-
nario is one in which the subrate data comes from sev-
eral sources which cross a frame boundary. The
selection of the framing bit remains identical to the byte
scenario. To maintain the virtual frame, some subrate
data must have the frame bit (FME) set, and some
must have them cleared. Operationally, there is no dif-
ference. Since the inputs and outputs are identified by
stream and time-slot addresses, charts from Appendix
B of this data sheet can be used to determine the FME
bit setting. Figure 15 below shows an example of virtual
framing for subrate connections.
FME settings for individual subrate pieces, in order to
maintain virtual frame integrity across the true frame
boundary, are based on the description in Appendix B
(all streams 8 Mbits/s).
5-7147F
Figure 15. Constant Delay/Minimum Delay Example
2.4.7 Example of a Practical Application
Three 16 kbits/s GSM voice channels are presented
with either 1 or 2 bits of HDLC/LAPD. The user wishes
to strip out the HDLC/LAPD information and pass
through the voice channels with minimum latency.
Specific requirements are listed below:
1.
The ability to extract 1 or 2 bits from any time slot
presented. The time slots are presented via T1/E1
or from the H.100 bus. The extracted bits will be
treated as an HDLC/LAPD channel and must be
presented separately to a host CPU.
2.
The ability to inject a 1 or 2 bit stream into any
time slot.
3.
The bit positions to be extracted/injected must be
programmable. In the case of injection, the
injected bits will overwrite the value of the bits pre-
viously occupying those positions.
4.
The ability to switch full time slots presented to it
while performing injection/extraction.
The terms
injection
and
extraction
are synonymous
with
packing
and
unpacking
.
Clearly, the applications for subrate switching are
numerous. In the 16 kbits/s GSM world alone, the
H.100 bus could be thought of as a 16,384 subrate
time-slot bus. Since the subrate is programmable on a
time slot by time-slot basis, mixed subrates are possi-
ble as well, even within a single time slot.
2.5 Clocking Section
The clocking section performs several functions which
are detailed in the following paragraphs. In general,
when the devices are in bus master mode, there will be
one or more companion devices which provide the
basic clock extraction and jitter attenuation from a
source (such as a trunk). As a slave, the devices can
work independently of, or in conjunction with, external
resources. Examples of different operating modes are
provided in Appendix A. Refer to Figure 16 for a block
diagram of the devices clocking section.
When the devices are used as bus masters, an input
clock of a tolerance of
±
32 ppm is required. This can
come from several sources. For example:
I
±
32 ppm crystal tolerance is the suggested value if
either the DPLL is used or fallback to the oscillator is
enabled while mastering the bus. Otherwise, a crys-
tal with a lesser tolerance can be used.
I
If a crystal is not used, a 16.384 MHz (
±
32 ppm toler-
ance or less) signal must be provided to the XTALIN
pin, and XTALOUT should be left unconnected.
I
The L_REF inputs can also be used and must con-
form to
±
32 ppm in a bus master situation.
FME = 0
VIRTUAL FRAME
I
O
FRAME BOUNDARY
FME = 1
FME = 1
TS
= –1
TS
= +2
TS
= +126
TS
= +1
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|---|---|
| T8105A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8100 | H.100/H.110 Interface and Time-Slot Interchanger |
| T8110 | Version History |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T810-400B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS |
| T8105A | 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers |
| T810-600B | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB |
| T810-600B | 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK |
| T810-600B-TR | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB |
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