參數(shù)資料
型號: T8102A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時隙Interchangers
文件頁數(shù): 30/112頁
文件大?。?/td> 1408K
代理商: T8102A
26
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.2 Local Bus Section
(continued)
2.2.3 Data Rates and Time-Slot Allocation
(continued)
Examples of how the memory is filled are found in Figure 7.
Note:
Again, the user needs only to provide stream and time-slot addresses; the devices will generate the internal
memory addresses.
Both the connection and data memories are filled using the same algorithm. In the case where group C is running
at 8.192 Mbits/s, group B is at 4.096 Mbits/s (or 2.048 Mbits/s), and group A is at 2.048 Mbits/s, then an additional
virtual memory space of 4 x 64 locations is created from unused locations in other parts of the memory.
5-6105F
Figure 7. Local Memory (T8100A, T8105 Only), Fill Patterns
TIME SLOT 0
TIME SLOT 2
TIME SLOT
4
TIME SLOT 1
TIME SLOT 3
TIME SLOT 5
TIME SLOT 0
TIME SLOT 1
TIME SLOT 2
TIME SLOT 0
TIME SLOT 2
TIME SLOT 4
TIME SLOT 1
TIME SLOT 3
TIME SLOT 5
STREAM
0—3
STREAM
4—7
STREAM
0—3
STREAM
4—7
STREAM
0—3
STREAM
4—7
STREAM
8—11
STREAM
8—11
GROUP A,
EVEN
TIME SLOTS
GROUP A,
ODD
TIME SLOTS
GROUP A,
ALL
TIME
SLOTS
64 TIME SLOTS
64 TIME SLOTS
GROUP A AT 8.192 Mbits/s
GROUPS B AND C OFF
GROUP A AT 4.096 Mbits/s
GROUP B AT 8.192 Mbits/s
AND GROUP C OFF
GROUP
B, EVEN
TIME
SLOTS
GROUP
B, ODD
TIME
SLOTS
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T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
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T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
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