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| 型號： | T8102A |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchangers |
| 中文描述： | H.100/H.110接口和時隙Interchangers |
| 文件頁數(shù)： | 19/112頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | T8102A |
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Lucent Technologies Inc.
15
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.1 Register/Memory Maps
In this section, a general overview of the registers and the indirect mapping to different memory spaces is
described. More detailed descriptions for using the registers in software can be found in Section 3.4 Using the
LAR, AMR, and IDR for Connections.
(Throughout this document, all registers are defined with the MSB on the left and the LSB on the right.)
2.1.1 Main Registers
The address bits are used to map a large memory space.
All registers default to 0 at powerup.
Table 8. Addresses of Programming Registers
2.1.2 Master Control and Status Register
Table 9. Master Control and Status Register
A1
0
0
1
1
A0
0
1
0
1
Symbol
MCR
LAR
AMR
IDR
Name/Description
Master Control and Status Register (read/write)
Lower Address Register—Lower Indirect Address (time slot) (write only)
Address Mode Register—Upper Address (stream) and Address Type (write only)
Indirect Data Register (read/write)
Symbol
MR
CER
SER
Bit
7
6
5
Name/Description
Master (Software) Reset
. A high reinitializes the registers.
Clock Error Reset
. A high resets the error bits of the CLKERR registers.
System Error Reset
. A high resets the error bits of the SYSERR register. (Note that MR,
CER, and SER are automatically cleared after the requested reset is complete.)
Active Page
. This bit identifies which of the double-buffered data memories are active. A
zero indicates buffer 0; a one indicates buffer 1. The AP identifies which data buffer is being
accessed during a write operation (i.e., input from local streams or input from H-bus).
H-Bus Enable
. On powerup or software reset, all H-bus pins (including clocks) are disabled.
HBE must be set high to reenable the 3-stated buffers.
Local Bus Enable
. Same function as HBE for local data outputs.
Local Clock Enable
. Enables all other local functions: clocks, frame groups, etc. (Note that
the TCLKOUT is disabled during a Master Reset and is unaffected by HBE, LBE, or LCE,
though there are control bits for this signal in the CKP register. See Section 2.5.8 Clock Con-
trol Register Definitions for a description of the CKP register.) 3-stated if disabled.
CAM Busy
. A status bit indicating microprocessor activity in any of the CAM blocks. A high
means that one (or more) of the CAMs is being accessed by the microprocessor. In most
cases, this bit will read low since there are many internal operational cycles dedicated to the
microprocessor, which allow it to finish quickly.
AP
4
HBE
3
LBE
LCE
2
1
CB
0
相關PDF資料 |
PDF描述 |
|---|---|
| T8105A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8100 | H.100/H.110 Interface and Time-Slot Interchanger |
| T8110 | Version History |
| T8301 | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T810-400B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS |
| T8105A | 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers |
| T810-600B | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復通態(tài)電流:120 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:TO-220AB |
| T810-600B | 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK |
| T810-600B-TR | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復通態(tài)電流:120 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:TO-220AB |
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