參數(shù)資料
型號： T8102A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁數(shù)： 69/112頁
文件大小： 1408K
代理商： T8102A
Lucent Technologies Inc.
65
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.8 The JTAG Test Access Port
(continued)
2.8.3 Elements of JTAG Logic
The signal TRST, which is used for resetting the JTAG TAP controller, must be asserted to make the simulation
model (VHDL or Verilog* or encrypted Verilog) operate. Since the TAP controller does not always power up in nor-
mal mode, the TPA controller has to be reset. Resetting the TAP controller is done by asserting TRST (brought low)
and keeping it low throughout the test.
Table 62. JTAG Scan Register
* Verilogis registered trademark of Cadence Design Systems, Inc.
Cell
66
67
68
0
69—76
1
77
78
79
80
81
82
83
84
85—88
44
89—96
97
98
45
99
100
46
101
43
102
42
103—108
41
109—120
63
Type
I
O
O
CC
Bdir
CC
I
O
I
I
I
I
I
I
O
CC
I
I
O
CC
O
O
CC
Bdir
CC
Bdir
CC
Bdir
CC
O
CC
Signal Name/Function
CK_3MHZIN
SYSERR
CLKERR
Controls cells 67:68
D[0:7]
Controls cells 69:76
RESTN
RDY
WRN
RDN
CSN
ALE
A0
A1
L_SC[0:3]
Controls cells 85:88
L_REF[0:7]
CK_4MHZIN
PRIREFOUT
Controls cell 98
TESTOUT1
REFCLK1O
Controls cells 99, 100
FROMDJAT
Controls cell 101
TODJAT
Controls cell 102
GP[5:0]
Controls cells 103—108
FGB[11:0]
Controls cells 109—120
Cell
Type
O
CC
Bdir
Bdir
Bdir
Bdir
CC
Bdir
CC
Bdir
CC
Bdir
Bdir
CC
Bdir
CC
Bdir
CC
Bdir
Bdir
CC
Bdir
CC
O
CC
O
CC
I
O
CC
Signal Name/Function
FGA[11:0]
Controls cells 121—132
C16N_MINUSA
C16N_PLUSA
C4N
C2
Controls cells 133—136
SCLKX2NA
Controls cell 137
SCLKA
Controls cell 138
CT_C8_BA
CT_FRAME_BNA
Controls cells 139—140
FRN_COMPA
Controls cell 141
CT_NETREF
Controls cell 142
CT_C8_AA
CT_FRAME_ANA
Controls cells 143—144
CT_D[0:31]
Controls cells 145—176
LDO[0:15]
Controls cells 177—192
XCS
Controls cell 193
LDI[0:15]
TCLKOUT
Controls cell 65
121—132
64
133
134
135
136
5
137
7
138
6
139
140
3
141
4
142
8
143
144
2
145—176
9—40
177—192
47—62
193
0
194—209
210
65
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T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
T810-600B 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
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