參數(shù)資料
型號: T8102A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時(shí)隙Interchangers
文件頁數(shù): 53/112頁
文件大?。?/td> 1408K
代理商: T8102A
Lucent Technologies Inc.
49
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional Description
(continued)
2.5 Clocking Section
(continued)
2.5.8 Clock Control Register Definitions
Table 46. CKM: Clocks, Main Clock Selection, 0x00
The first register, 0x00, is the clock main (CKM) register. There are ten registers to control the various aspects of
clocking.
* Selecting A clocks synchronizes the devices to CT_C8A and /CT_FRAMEA; selecting B clocks synchronizes the devices to CT_C8B and
/CT_FRAMEB; MVIPuses /C4, C2, and /FR_COMP; H-MVIPuses /C16+/–, /C4, C2, and /FR_COMP; SC2 uses SCLKX2 and /FR_COMP;
SC4/8 requires SCLK, SCLKX2, and /FR_COMP MC-1 fallback clocks use the same inputs and state machine as the A clocks and B clocks
with an inversion selected from register CKP A pictorial view of the various clocks is shown in Section 4.8.1 Clock Alignment.
Reg
CKM
R/W
Bit 7
PAE
Bit 6
PAS
Bit 5
CCD
Bit 4
CKI
Bit 3
Bit 2
Bit 1
Bit 0
CKSEL
Symbol
PAE
Bit
7
Description
Phase Alignment Enable.
PAE = 0,
PAE = 1,
Phase Alignment.
PAS = 0,
PAS = 1,
The CCD bit is the compatibility clock direction. This controls the I/O for the compatibility
clocks /C16+/–, /C4, C2, SCLK, SCLKX2, and /FR_COMP (compatibility frame). The user can
think of the CCD bit (in some respects) as a master/slave select for the compatibility clocks,
though other registers require proper setup to establish true master or slave operation. The
devices will assume control of this bit during a fallback if the previously designated compatibil-
ity clock master fails.
CCD = 0,
Slave, monitors compatibility signals.
CCD = 1,
Master, drives compatibility signals.
Note:
If bit 4 of the programmable clocks register, CKP is low, then the state machines of the
A clock and B clock will assume this is an MC-1 system and interpret the clocks as
/C4(L/R) and FRAME(L/R). If this bit is high, then it interprets the clocks as C8(A/B)
and FRAME(A/B).
CKI is used to invert the output of the clock selector, i.e., the signal which feeds the main
divider, resource divider, and DPLL:
CKI = 0,
Normal.
CKI = 1,
Invert.
3—0 The decode for the clock selector (CKSEL) is illustrated below. These selections determine
which input state machine is utilized*:
CKSEL = 0000,
Internal oscillator.
CKSEL = 0001,
CT_NETREF1 or CT_NETREF2 (CON register bit 5 selects:
if 0 then CT_NETREF1 is selected, if 1 CT_NETREF2).
CKSEL = 0010,
A clocks (C8A & FRAMEA); ECTF or MC-1.
CKSEL = 0011,
B clocks (C8B & FRAMEB); ECTF or MC-1.
CKSEL = 0100,
MVIPis selected, /C4 is selected as the clock reference for PLL #1.
CKSEL = 0101,
H-MVIP s selected, /C16 is selected as the clock reference for
PLL #1.
CKSEL = 0110,
SC-Bus, 2 MHz. SCLKX2 is selected as the clock reference for
PLL #1.
CKSEL = 0111,
SC-Bus, 4 MHz or 8 MHz. SCLK is selected as the clock
reference for PLL #1.
CKSEL = 1000—1111 Selects local references 0—7. When bit 4 of the CON register is set,
these bits select pairs of synchronized inputs.
Retains frequency lock without phase alignment.
Enables phase alignment.
PAS
6
Phase alignment, snap.
Phase alignment, slide.
CCD
5
CKI
4
CKSEL
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