參數(shù)資料
型號： T8102A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時隙Interchangers
文件頁數(shù)： 91/112頁
文件大小： 1408K
代理商： T8102A
Lucent Technologies Inc.
87
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
4 Electrical Characteristics
(continued)
4.8 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)
(continued)
4.8.4 ac Electrical Characteristics, Timing, H-Bus (H.100 Spec., Rev. 1.0)
Table 76. ac Electrical Characteristics, Timing, H-Bus (H.100 Spec., Rev. 1.0)
Symbol
—
tC8P
tC8H
tC8L
tSAMP
tDOZ
tZDO
tDOD
tDV
tDIV
tFP
tFS
tFH
Φ
Parameter
Min
0.25
Typ
—
—
—
—
90
—
—
—
—
—
122
—
—
—
Max
2
Unit
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1, 2, 4
2, 4, 5
2, 4, 6
2, 4, 6
2, 4, 9
2, 3, 4, 7, 11
2, 3, 4, 7, 11
2, 3, 4, 7
2, 3, 4, 8, 10
2, 4
2, 4
2, 4
2, 4
12
Clock Edge Rate (all clocks)
Clock CT_C8 Period
Clock CT_C8 High Time
Clock CT_C8 Low Time
Data Sample Point
Data Output to HiZ Time
Data HiZ to Output Time
Data Output Delay Time
Data Valid Time
Data Invalid Time
/CT_FRAME Width
/CT_FRAME Setup Time
/CT_FRAME Hold Time
Phase Correction
122.066 –
Φ
49 –
Φ
49 –
Φ
—
–20
0
0
0
102
90
45
45
0
122.074 +
Φ
73 +
Φ
73 +
Φ
—
0
22
22
69
112
180
90
90
10
1. The rise and fall times are determined by the edge rate in V/ns. A maximum edge rate is the fastest rate at which a clock transitions.
CT_NETREF has a separate requirement. (See Section 2.5 Clocking Section.)
2. Measuring conditions, data lines: VTH (threshold voltage) = 1.4 V, VHI (test high voltage) = 2.4 V, VLO (test low voltage) = 0.4 V, input sig-
nal edge rate = 1 V/ns measuring conditions, clock and frame lines: Vt+ (test high voltage) = 2.0 V, Vt– (test low voltage) = 0.6 V, input sig-
nal edge rate = 1 V/ns.
3. Test load—200 pF.
4. When RESET is active, every output driver is 3-stated.
5. tC8P minimum and maximum are under free-run conditions assuming ±32 ppm clock accuracy.
6. Noncumulative, tC8P requirements still need to be met.
7. Measured at the transmitter.
8. Measured at the receiver.
9. For reference only.
10. tDV = maximum clock cable delay + maximum data cable delay + maximum data HiZ to output time = 12 ns + 35 ns + 22 ns = 69 ns. Maxi-
mum clock cable delay and maximum data cable delay are worst-case numbers based on electrical simulation.
11. tDOZ and tZDO apply at every time-slot boundary.
12. F (phase correction) results from PLL timing corrections.
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