參數(shù)資料
型號: T8102A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時(shí)隙Interchangers
文件頁數(shù): 36/112頁
文件大?。?/td> 1408K
代理商: T8102A
32
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
2 Architecture and Functional
Description
(continued)
2.3 H-Bus Section
(continued)
2.3.2 CAM Operation and Commands
The three CAMs operate in parallel. Each CAM’s com-
parand field is compared with the state counter (Sec-
tion 2.2.5 State Counter Operation) which holds the
existing stream and time-slot value*. If there is a match,
the CAM issues a hit. If there is more than one match,
then it is considered a multiple hit. Likewise, no match
is a miss. As a part of the state counter, a bit is toggled
for read/write. The read/write bit is stored in the CAM,
so it becomes part of the value to be compared. If the
comparison for a write yields a hit, then there is a
request for write access to the data memory for the
incoming data from the H-bus. If the comparison for a
read yields a hit, then there is a request for a read
access from the data memory for outgoing data to the
H-bus. A miss implies no action. Any multiple hit within
one CAM block is treated as a controlled error although
it is not reported. The action taken is to acknowledge
the hit which corresponds to the lowest physical
address of the CAM. A multiple hit is assigned to be
more than one valid connection. These are prioritized
such that the match with the lowest physical address
(i.e., closest to CAM location 0x0) is the address which
is processed. Thus, errors are handled in a controlled
manner. Multiple hits can occur because multiple loca-
tions are assigned to the same time slot. Good soft-
ware and careful coding can help avoid this problem. A
controlled error has no impact on performance, and the
CAM contents are not changed as a result of the error.
The data SRAMs are actually dual-port register files
which will process both writes and reads on each clock
cycle of the clock. The devices can process a read and
write request from each CAM and two microprocessor
requests during the time of one address comparison.
Due to the fixed order of operations, the data SRAM
cannot overflow or underflow like the CAMs. The timing
is shown in Figure 10.
* As mentioned in Section 2.2.5 State Counter Operation, for each
stream and time-slot value, the state counter goes through four
functional states for each stream and time slot. These states are
used to synchronize the CAMs, pipeline register files, data SRAMs,
and microprocessor accesses just as they are used to synchronize
local memory operations and the frame groups. (Microprocessor
accesses to the memories are initiated asynchronously, though the
actual microprocessor cycles are synchronous.)
相關(guān)PDF資料
PDF描述
T8105A H.100/H.110 Interface and Time-Slot Interchangers
T8100 H.100/H.110 Interface and Time-Slot Interchanger
T8110 Version History
T8301 T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP
T8302 T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T810-400B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS
T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
T810-600B 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流(在 VDRM IDRM 下):5 uA 開啟狀態(tài)電壓: 保持電流(Ih 最大值):45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
T810-600B-TR 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流(在 VDRM IDRM 下):5 uA 開啟狀態(tài)電壓: 保持電流(Ih 最大值):45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB