參數(shù)資料
型號(hào)： T8102A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁數(shù)： 77/112頁
文件大?。?/td> 1408K
代理商： T8102A
Lucent Technologies Inc.
73
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
3 Using the TSI Devices
(continued)
3.4 Using the LAR, AMR, and IDR for
Connections
3.4.1 Setting Up Local Connections (T8100A, T8105
Only)
Local connections require a physical location in the
local connection memory corresponding to the output
stream and time slot. The location contains a pointer to
a local data memory location which holds the actual
data that has come in or will be sent out. The local
memories are based on 1024 locations, so 10 bits are
required to specify the physical memory location where
a connection is placed or where data is stored. To sim-
plify the programming, the user supplies 11 bits in a
stream and time-slot format, which is converted by the
devices to the appropriate physical location. Relative to
describing a connection, a data memory location corre-
sponds with the FROM stream and time slot, and a
connection memory location corresponds with the TO
stream and time slot. To program a connection, the
user loads the data memory location into the connec-
tion memory location, effectively identifying where the
data resides.
The user programs 7 bits of the LAR for the time-slot
value (or 8 bits for pattern mode) and the lowest 4 bits
of the AMR for the stream value; these will then be con-
verted to the physical memory address. The upper bits
of the AMR select which field in the connection mem-
ory is being written into. Since the connection informa-
tion itself is 15 bits, two transfers (i.e., two fields) must
be made to the address in the connection memory.
In each case, the transfer is an indirect write of data to
the indirect data register, the IDR: The first transfer is
the lowest 7 bits (time-slot address) of the desired data
memory location. It is placed in the IDR after the LAR
and AMR have been set up with the appropriate con-
nection address.
Table 69 illustrates the decoding of the time-slot bits
(address value in the table refers to the hex value of the
7 bits comprising time slot).
When programming the registers for fallback, the CKS
and CKW registers should be programmed last.
Table 69. Time-Slot Bit Decoding
Address
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
:
0x1E
0x1F
0x20
:
0x3E
0x3F
0x40
:
0x7E
0x7F
2 Mbits/s
Time Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
:
30
31
NA
:
NA
NA
NA
:
NA
NA
4 Mbits/s
Time Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
:
30
31
32
:
62
63
NA
:
NA
NA
8 Mbits/s
Time Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
:
30
31
32
:
62
63
64
:
126
127
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T810-400B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS
T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
T810-600B 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
T810-600B-TR 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
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