參數(shù)資料
型號(hào): T8102A
英文描述: H.100/H.110 Interface and Time-Slot Interchangers
中文描述: H.100/H.110接口和時(shí)隙Interchangers
文件頁(yè)數(shù): 14/112頁(yè)
文件大?。?/td> 1408K
代理商: T8102A
10
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
1 Product Overview
(continued)
1.3 Pin Information
(continued)
Table 4. Pin Descriptions: Microprocessor Interface Pins
Table 5. Pin Descriptions: JTAG Pins
Symbol
RESET
Pin
24
Ball
J1
Type
I
Name/Description
Master Reset (Active-Low).
See Section 3.1 Resets. 50 k
internal pull-
up.
Microprocessor Interface, Address Lines.
Internal 20 k
pull-down.
A[1:0]
31—30 L4,
L2
H1,
H2,
G1,
H3,
G2,
F1,
G4,
G3
L1
K3
K2
I
D[7:0]
22—15
I/O
Microprocessor Interface, Data Lines.
8 mA drive, 50 k
internal pull-up.
ALE
CS
29
28
27
I
I
I
Address Latch Enable.
Internal 20 k
pull-down.
Chip Select (Active-Low).
50 k
internal pull-up.
Read Strobe (IntelMode [Active-Low]), Data Strobe (Motorola [Active-
Low]).
50 k
internal pull-up.
Write Strobe (Intel[Active-Low]), Read/Write Select (Motorola [Active-
Low]).
50 k
internal pull-up.
Data Ready (Intel), Data Transfer (Motorola [Active-Low]).
8 mA, open drain (user should add pull-up to this line).
RD (DS)
WR (R/W)
26
K1
I
RDY (DTACK)
25
J3
O
Symbol
TCLK
TMS
TDI
TDO
Pin
9
8
7
6
5
Ball
E3
F4
D2
C1
E4
Type
I
I
I
O
I
Name/Description
JTAG Clock Input.
JTAG Mode Select.
50 k
internal pull-up.
JTAG Data Input.
50 k
internal pull-up.
JTAG Data Output.
8 mA drive, 3-state.
JTAG Reset (Active-Low).
50 k
internal pull-up.
TRST
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