- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371179 > T8102A H.100/H.110 Interface and Time-Slot Interchangers PDF資料下載
參數(shù)資料
| 型號： | T8102A |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchangers |
| 中文描述： | H.100/H.110接口和時隙Interchangers |
| 文件頁數(shù)： | 6/112頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | T8102A |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
2
Lucent Technologies Inc.
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
Table of Contents
Contents
Page
1 Product Overview.....................................................1
1.1 Features..............................................................1
1.2 Description..........................................................1
1.3 Pin Information....................................................6
1.4 AmbassadorTSI Architecture...........................12
1.5 Selecting Between T8105, T8102, T8100A,
and T8100.........................................................12
1.6 Enhanced Local Stream Addressing.................12
1.7 Full H.100 Stream Address Support .................12
1.8 Onboard PLLs and Clock Monitors...................12
1.9 Phase Alignment of Referenced and
Generated Frames............................................12
1.10 Interfaces ........................................................13
1.10.1 Microprocessors........................................13
1.10.2 Framing Groups ........................................13
1.10.3 General-Purpose Register and I/O............13
1.11 Applications.....................................................13
1.12 Application Overview ......................................13
2 Architecture and Functional Description.................13
2.1 Register/Memory Maps.....................................15
2.1.1 Main Registers ............................................15
2.1.2 Master Control and Status Register............15
2.1.3 Address Mode Register...............................16
2.1.4 Control Register Memory Space.................17
2.2 Local Bus Section .............................................23
2.2.1 Constant Frame Delay and Minimum
Delay Connections......................................24
2.2.2 Serial and Parallel.......................................24
2.2.3 Data Rates and Time-Slot Allocation ..........25
2.2.4 LBS: Local Stream Control, 0x0C ...............28
2.2.5 State Counter Operation .............................29
2.2.6 Software to Reset the Local Connection
Memory.......................................................29
2.3 H-Bus Section...................................................30
2.3.1 Memory Architecture...................................30
2.3.2 CAM Operation and Commands.................32
2.3.3 H-Bus Access..............................................36
2.3.4 L-Bus Access ..............................................37
2.3.5 H-Bus Rate Selection and Connection
Address Format...........................................37
2.4 Subrate Switching for the Ambassador
Family................................................................39
2.4.1 Description, Operation, and Application......39
2.4.2 Definitions ...................................................39
2.4.3 Subrate Switching on H.100/H.110.............39
2.4.4 Using the Existing Architecture ...................40
2.4.5 Limitations...................................................42
2.4.6 Minimum vs. Constant Delay.......................43
2.4.7 Example of a Practical Application..............43
2.5 Clocking Section ...............................................43
2.5.1 Clock and NETREF Selection.....................45
Contents
Page
2.5.2 Dividers and Rate Multipliers...................... 45
2.5.3 State Machines........................................... 45
2.5.4 Frame Sync................................................ 45
2.5.5 Bit Sliding (Frame Locking)........................ 45
2.5.6 MTIE........................................................... 46
2.5.6.1 MTIE Compliance ................................. 46
2.5.6.2 Relationship of the Bit Slider to MTIE... 46
2.5.6.3 Using the Bit Slider ............................... 46
2.5.7 Clock Fallback............................................ 47
2.5.8 Clock Control Register Definitions.............. 49
2.5.8.1 Basic Fallback Mode............................. 54
2.5.8.2 CKMD, CKND, CKRD: Clocks, Main,
NETREF, Resource Dividers
0x07, 0x08, 0x09.................................. 55
2.5.9 LREF Pairing.............................................. 57
2.5.9.1 LREF Port Configuration....................... 57
2.5.9.2 Operation.............................................. 58
2.5.9.3 Example of LREF Pairing on a T8100A 58
2.5.9.4 Advantages of LREF Pairing ................ 58
2.6 Interface Section.............................................. 58
2.6.1 Microprocessor Interface............................ 58
2.6.2 General-Purpose Register.......................... 58
2.6.3 Framing Groups ......................................... 59
2.6.3.1 Frame Group Timing............................. 60
2.7 Error Registers................................................. 62
2.8 The JTAG Test Access Port............................. 64
2.8.1 Overview of the JTAG Architecture............ 64
2.8.2 Overview of the JTAG Instructions............. 64
2.8.3 Elements of JTAG Logic............................. 65
2.9 Testing and Diagnostics................................... 66
2.9.1 Testing Operations..................................... 66
2.9.2 Diagnostics................................................. 66
3 Using the TSI Devices........................................... 69
3.1 Resets.............................................................. 69
3.1.1 Hardware Reset ......................................... 69
3.1.2 Software Reset........................................... 69
3.1.3 Power-On Reset......................................... 69
3.2 Device Settings ................................................ 70
3.2.1 Architecture................................................ 70
3.3 Basic Connections ........................................... 71
3.3.1 LPUE Control Pins ..................................... 71
3.3.2 H.100/H.110 Data Pin Series
Termination ................................................ 71
3.3.3 H.110 Hot Swap ......................................... 71
3.3.4 Physical Connections for H.100................. 72
3.3.5 Physical Connections for H.110................. 72
3.3.6 PC Board BGA Considerations.................. 72
3.4 Using the LAR, AMR, and IDR for
Connections ..................................................... 73
3.4.1 Setting Up Local Connections (T8100A,
T8105 Only)................................................ 73
相關PDF資料 |
PDF描述 |
|---|---|
| T8105A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8100 | H.100/H.110 Interface and Time-Slot Interchanger |
| T8110 | Version History |
| T8301 | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| T8302 | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T810-400B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS |
| T8105A | 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers |
| T810-600B | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復通態(tài)電流:120 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:TO-220AB |
| T810-600B | 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK |
| T810-600B-TR | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復通態(tài)電流:120 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:TO-220AB |
發(fā)布緊急采購，3分鐘左右您將得到回復。