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參數(shù)資料
| 型號(hào)： | T8102A |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchangers |
| 中文描述： | H.100/H.110接口和時(shí)隙Interchangers |
| 文件頁數(shù)： | 75/112頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | T8102A |
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Lucent Technologies Inc.
71
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
3 Using the TSI Devices
(continued)
3.3 Basic Connections
At a minimum, the devices require power, ground, and
a 16.384 MHz crystal (or 16.384 MHz oscillator). It is
also recommended that the internal PLLs be treated as
other analog circuits are, so the user should provide
the appropriate filtering between the PLL1V
DD
and V
DD
pins (as well as PLL2V
DD
and V
DD
pins). The RDY pin
is operated as an open collector output. It is actively
driven low or into 3-state. The user should apply a pull-
up (e.g., 10 k
) to maintain standard microprocessor
interfacing. It is recommended that the 10 k
be tied to
3.3 V (since the device’s nominal V
OH
is 3.3 V), but the
resistor may also be tied up to 5 V without damaging
the device. A 33
μ
F tantalum capacitor and 25
series
resistor are necessary to provide VCO stability in the
PLLs. PLL connections are shown in Figure 20.
3.3.1 LPUE Control Pins
A list of 46 pull-ups which LPUE controls is shown in
the table below. LPUE has a pull-up attached, so the
default is pull-ups enabled.
LPUE is used as an assist to meet the CompactPCI*
Hot Swap specification. During live insertion/removal,
the only devices that should be on are the power man-
ager and interface parts (PCI interface attached to
J1, H.110 interface attached to J4 on a CompactPCI
chassis). Without the LPUE, anything connected to the
T810x would get current flow from the early power
through the pull-up resistors. When those parts power-
up (late power), they already have current flowing
through the I/O and latch-up may occur. Quick-switch
parts were used for isolation on the earlier T8100
device, so when the T8100A/02/05 were designed,
LPUE was added to break the current flow and elimi-
nate the isolation switches. LPUE is typically tied to a
pin on the CompactPCIpower manager so that the pull
ups are re-enabled with backside power turning on.
Table 68. LPUE Control Pins
5-6114.aF
Figure 20. External Connection to PLLs
3.3.2 H.100/H.110 Data Pin Series Termination
All data bus lines must have a 24
series resistor,
even if only data lines 16—31 are used.
3.3.3 H.110 Hot Swap
When using the Ambassadorin a hot-swap application,
it is acceptable to power the PLLs after applying power
to the chip. All hot-swap requirements are governed by
the CompactPCIHot Swap specification.
* CompactPCI is a registered trademark of the PCI Industrial Com-
puter Manufacturers Group.
Pin
1
Name
3MHzIn
D[7:0]
Pin
54
64
65
Name
4MHzIn
FromDJAT
ToDJAT
GP[5:0]
LDI[7:0]
LDI[15:8]
22—15
24
26
27
28
45—38
RESET
WR
RD
CS
L_REF[7:0]
66—71
192—185
201—194
T8100A
T8102
T8105
RDY
PLLV
DDS
PLLGND
S
V
DD
= 3.3 V
25
TANTALUM
10 k
50 k
NETREF,
C8s, AND
FRAMES
33
μ
F
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T810-400B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS |
| T8105A | 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers |
| T810-600B | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB |
| T810-600B | 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK |
| T810-600B-TR | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB |
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