參數(shù)資料
型號(hào)： T8102A
英文描述： H.100/H.110 Interface and Time-Slot Interchangers
中文描述： H.100/H.110接口和時(shí)隙Interchangers
文件頁(yè)數(shù)： 5/112頁(yè)
文件大小： 1408K
代理商： T8102A
Advance Data Sheet
November 1999
Ambassador
TM
T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
1 Product Overview
1.1 Features
I
Complete solution for interfacing board-level cir-
cuitry to the H.100 telephony bus
I
H.100 compliant interface; all mandatory signals
I
Programmable connections to any of the 4096 time
slots on the H.100 bus
I
Up to 16 local serial inputs and 16 local serial
outputs, programmable for 2.048 Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s operation per CHI
specifications
I
Programmable switching between local time slots,
up to 1024 connections
I
Subrate switching of nibbles, dibits, or bits
I
Backward compatible to T8100 through software
I
Programmable switching between local time slots
and H.100 bus, up to 512 (T8102, T8105 only)
connections
I
Choice of frame integrity or minimum latency
switching on a per-time-slot basis
— Frame integrity to ensure proper switching of
wideband data
— Minimum latency switching to reduce delay in
voice channels
I
On-chip phase-locked loop (PLL) for H.100, MVIP*,
or SC-Bus clock operation in master or slave clock
modes
I
Serial TDM bus rate and format conversion
between most standard buses
I
Optional 8-bit parallel input and/or 8-bit parallel
output for local TDM interfaces
I
High-performance microprocessor interface
— Provides access to device configuration regis-
ters and to time-slot data
— Supports both Motorola
nonmultiplexed and
Intel
multiplexed/nonmultiplexed modes
I
Two independently programmable groups of up to
12 framing signals each
I
Devices available in 0.25 micron technology
I
3.3 V supply with 5 V tolerant inputs and TTL-com-
patible outputs
I
Boundary-scan testing support
I
208-pin, plastic SQFP package
I
217-ball BGA package (industrial temperature
range)
1.2 Description
These products in the AmbassadorT8100 family pro-
vide a complete time-slot switch and an interface for
the H.100/H.110 time-division multiplexed (TDM)
buses. The T8100 family includes devices with hier-
archical switching as well as a capacity of up to 512
local to H.100 connections. The hierarchical switch-
ing allows up to 1024 local connections without using
H.100 bus bandwidth. The family also includes the
T8102 device for a low-cost solution in nonhierarchi-
cal systems.
All three TSI chips are backward compatible with the
bus standards MVIP-90 and Dialogics
§
SC-Bus, as
well as supporting the newer standards, H-MVIPand
ECTF H.100. Other features include a built-in PLL for
H.100, MVIP or SC-Bus clock operation in master or
slave clock modes and two independently program-
mable groups of up to 12 framing signals each. Pack-
aged in both a 208-pin SQFP and a 217-ball BGA,
the T8100 TSI devices provide an economic solution
for the computer telephony market.
* MVIP is a registered trademark of GO-MVIP Inc.
Motorolais a registered trademark of Motorola, Inc.
Intelis a registered trademark of Intel Corporation.
§ Dialogic s a registered trademark of Dialogic Corporation.
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參數(shù)描述
T810-400B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS
T8105A 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers
T810-600B 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
T810-600B 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK
T810-600B-TR 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復(fù)通態(tài)電流:120 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220AB
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