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參數資料
| 型號： | T8102A |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchangers |
| 中文描述： | H.100/H.110接口和時隙Interchangers |
| 文件頁數： | 73/112頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | T8102A |
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Lucent Technologies Inc.
69
Advance Data Sheet
November 1999
H.100/H.110 Interfaces and Time-Slot Interchangers
Ambassador T8100A, T8102, and T8105
3 Using the TSI Devices
3.1 Resets
3.1.1 Hardware Reset
A hardware reset utilizes the (active-low) RESET pin.
On activation, it immediately places all outputs into
3-state. Individual output sections must be re-enabled
by setting the appropriate bits high in the MCR register.
Internally, the local memory (T8100A, T8105 only) is in
an undefined state, all CAM empty bits are set, all state
machines are reset, and all registers are cleared to
zero.
3.1.2 Software Reset
This is accomplished by setting the MSB of the master
control and status register (see Section 2.1.2 Master
Control and Status Register). The local and H-bus con-
nections are rendered invalid, all registers are cleared
except MCR, CLKERR1, CLKERR2, CLKERR3, and
SYSERR (these registers are cleared with separate
MCR control bits); the state machines are also reset.
Writing the value 0xE0 to the MCR is a full software
reset. Writing 0x0E enables all pin groups (though indi-
vidual pins still require setup). This soft reset is clocked
by the crystal.
3.1.3 Power-On Reset
No power-on reset is available. It is expected that the
host microprocessor or applications board will provide
an external control to the RESET pin for performing a
hardware reset. The PLLs must not be enabled prior to
establishing a stable supply voltage. There are two
methods to accomplish this:
I
Tie the En1 and En2 pins to the same line that drives
the RESET, which forces the PLLs into an off condi-
tion while the devices reset asynchronously.
I
Add external capacitors from En1 to ground and from
En2 to ground. (The values of the capacitors should
be 1 μF or greater.) The capacitors will form RC cir-
cuits with the En1 and En2 internal pull-ups and will
charge up to enable the PLLs after several millisec-
onds. The RC circuit affects the power-on reset for
the PLLs. The long rise time provides some delay.
相關PDF資料 |
PDF描述 |
|---|---|
| T8105A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8100 | H.100/H.110 Interface and Time-Slot Interchanger |
| T8110 | Version History |
| T8301 | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| T8302 | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
相關代理商/技術參數 |
參數描述 |
|---|---|
| T810-400B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HIGH PERFORMANCE TRIACS |
| T8105A | 制造商:AGERE 制造商全稱:AGERE 功能描述:H.100/H.110 Interface and Time-Slot Interchangers |
| T810-600B | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復通態(tài)電流:120 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:TO-220AB |
| T810-600B | 制造商:STMicroelectronics 功能描述:TRIAC 8A 600V D-PAK |
| T810-600B-TR | 功能描述:雙向可控硅 8A TRIACS RoHS:否 制造商:STMicroelectronics 開啟狀態(tài) RMS 電流 (It RMS):16 A 不重復通態(tài)電流:120 A 額定重復關閉狀態(tài)電壓 VDRM:600 V 關閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開啟狀態(tài)電壓: 保持電流（Ih 最大值）:45 mA 柵觸發(fā)電壓 (Vgt):1.3 V 柵觸發(fā)電流 (Igt):1.75 mA 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:TO-220AB |
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