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| 型號(hào)： | TMUX03155 |
| 英文描述： | TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer |
| 中文描述： | TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器 |
| 文件頁(yè)數(shù)： | 10/120頁(yè) |
| 文件大小： | 1542K |
| 代理商： | TMUX03155 |
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10
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Pin Information
(continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.
I = input, O = output, I/O = bidirectional signal, I
d
= input with internal pull-down (~20 kW), I
u
= input with internal pull-up (~100 kW), I
diff
or
O
diff
= differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or out-
puts. LVDS = low-voltage differential signal.
Pin
*
Symbol
Type
Name/Description
Transmit Direction Signals
Transmit High-Speed Serial Clock Input.
The transmit clock can
either be 155.52 MHz (serial), 38.88 MHz (nibble), or 19.44 MHz
(byte).
Center Tap for Transmit High-Speed Serial Clock Input.
The cen-
ter tap input provides for center-tapped common-mode termination.
This input should be terminated through an external capacitor to
ground (approximately 0.1 μF).
Transmit High-Speed Serial Sync Input.
The transmit sync signal
is active during J0 time (8 kHz), J11 time, and V11 time (2 kHz). This
signal is active-high and is optional. (See Figure 16 on page 112 for
details.)
Center Tap for Transmit High-Speed Serial Sync Input.
The cen-
ter tap input provides for center-tapped common-mode termination.
This input should be terminated through an external capacitor to
ground (approximately 0.1 μF).
Transmit High-Speed Clock Input
. The transmit clock can either be
38.88 MHz (nibble) or 19.44 MHz (byte).
Transmit High-Speed Sync Input.
The transmit sync signal is active
during J0 time (8 kHz), J11 time, and V11 time (2 kHz). This signal is
active-high and is optional.
Transmit Low-Speed Output Clock.
The STS-1/AU-3 clock will be
19.44 MHz.
Transmit Low-Speed Synchronous Payload Envelope (SPE)
.
The
STS-1/AU-3 SPE signal is low when the transport overhead is on the
input bus (TLSDATA[7:0]I). (See Figure 18 on page 116 for details.)
Transmit Low-Speed J0, J1, and V1 Time Signal.
J0 time is
defined when TLSSPEO is a logic 0, TLSJ0J1V1TIMEO is a logic 1,
TLSV1TIMEO is a logic 0, and the J0 byte is on the input bus. J1 time
is defined when TLSSPEO is a logic 1, TLSJ0J1V1TIMEO is a logic
1, TLSV1TIMEO is a logic 0, and J11 is on the input bus. (See Figure
18 on page 116 for details.)
Transmit Low-Speed V1 Time.
This signal is active-high when the
current frame contains the V1 byte. V1 time is defined when
TLSSPEO is a logic 1, TLSJ0J1V1TIMEO is a logic 1, and
TLSV1TIMEO is a logic 1. (See Figure 18 on page 116 for details.)
Transmit Low-Speed Data.
TLSDATA7I is the most significant bit of
the input byte. (See Figure 18 on page 116 for details.)
143, 142
THSSCLKIT/C
I
diff
LVDS
145
CTAP_THSSCLKI
I
140, 139
THSSJ0J1V1IT/C
I
diff
LVDS
141
CTAP_THSSJ0J1V1I
I
148
THSCLKI
I
d
150
THSJ0J1V1I
I
d
172
TLSCLKO
O
174
TLSSPEO
O
171
TLSJ0J1V1TIMEO
O
173
TLSV1TIMEO
O
170, 169,
167—162
TLSDATA[7:0]I
I
d
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