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| 型號(hào)： | TMUX03155 |
| 英文描述： | TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer |
| 中文描述： | TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器 |
| 文件頁(yè)數(shù)： | 24/120頁(yè) |
| 文件大?。?/td> | 1542K |
| 代理商： | TMUX03155 |
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24
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Receive Direction Overview
(continued)
Input Retime
The device accepts either a serial 155.52 MHz-Mbits/s, nibble 38.88 MHz-Mbits/s, or byte parallel 19.44 MHz-
Mbits/s clock-data STS-3/STM-1 (AU-4) input. This is controlled by writing to
RHSPTYPE[1:0], 0x55
. The user can
configure which edge of the clock to use to retime the data.
RHSEDGE, 0x55
= 1 uses the rising edge;
RHSEDGE
= 0 uses the falling edge. If in nibble or parallel mode, an odd/even parity bit (
RHSVOEPAR, 0x55
) is verified per
transfer (
RHSPARE
,
RHSPARM, 0x0A, 0x13
), otherwise, this indicator is disabled.
Clock and Data Recovery
The device provides an optional clock and data recovery circuit (CDR) on the serial STS-3/STM-1(AU-4) input. The
CDR aligns the STS-3/STM-1 data signal to a local clock and then outputs a retimed data and clock signal. The
input data and local clock rates need not be synchronous. The CDR only works at the nominal 155 Mbits/s rate and
uses the high-speed transmit input clock (THSSCLKIT/C) as a reference for the local clock. The CDR is enabled by
the
RHSPORCDRSEL
bit,
0x57
.
STS-3/STM-1 (AU-4) Framing
The device will frame on the input STS-3/STM-1 (AU-4) signal. The state of the framer (
RHSOOF
), as well as any
changes to this state (
RHSOOFD
,
RHSOOFM, 0x0A, 0x13
), will be reported. A loss-of-frame (
RHSLOF, 0x1B
)
state bit, as well as any changes to this state (
RHSLOFD
,
RHSLOFM, 0x0A, 0x13
), will be reported.
Framing Algorithm
The 32-bit (A1-2, A1-3, A2-1, A2-2) framing pattern will be used in the frame detection. The device will be consid-
ered out of frame until two successive framing patterns separated in time by 125 μs occur without framing byte
errors.
The device will be considered in frame until five (SDH)/four (SONET)
successive frames separated in time by
125 μs occur with errored framing patterns. If the framer transitions to the out-of-frame state, the framer will remain
synchronized to the last known frame boundary or the latest detected unerrored framing pattern.
The device will be considered in the loss-of-frame state (LOF) when an OOF condition persists for 24
consecutive
frames (3 ms). The device will transition out of the LOF state after receiving 24 consecutive frames with the correct
framing patterns spaced 125 μs apart and the OOF condition is clear.
Loss of Signal
The device will detect a loss-of-signal condition by monitoring a unique input signal pin (RHSLOSEXTI) or detect-
ing a continuous all-zeros/all-ones pattern for 51.44 ns to 105 μs in 51.44 ns steps (
LOSDETCNT[10:0], 0x58—
0x59
) before data is descrambled. To recover from the LOS state receiving two consecutive frames with the correct
framing pattern spaced 125 μs apart without an incoming LOS all-zeros/ones pattern will cause an LOS state to be
cleared. This recovery applies to both internal and external LOS failure causes. The device will report this condition
to the microprocessor interface (
RHSLOS
,
RHSLOSD
,
RHSLOSM, 0x1B, 0x0A, 0x13
).
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