參數(shù)資料
型號(hào)： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器
文件頁數(shù)： 6/120頁
文件大?。?/td> 1542K
代理商： TMUX03155
List of Tables
(continued)
Contents
Page
6
Agere Systems Inc.
Preliminary Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Table 52. Register 77: Transmit High-Speed Error Insert Control Parameters (R/W) .........................................73
Table 53. Register 78: Transmit High-Speed Error Insert (R/W) .........................................................................73
Table 54. Register 79: Receive/Transmit TOAC Control (R/W) ..........................................................................74
Table 55. Registers 80, 81: Transmit TOAC Control (R/W) ................................................................................75
Table 56. Register 83, 84: Transmit High-Speed STS-3/STM-1 Output Frame Offset (R/W) .............................77
Table 57. A1-1 Alignment Parameters ................................................................................................................80
Table 58. BITCNT Alignment Table .....................................................................................................................80
Table 59. Register 85: Receive High/Low-Speed Port Control (R/W) .................................................................81
Table 60. Register 86: Receive J1 and Receive Low-Speed Port Select Control (R/W) .....................................82
Table 61. Register 87: STS-1/AU-3 Receive Control Bits (R/W) .........................................................................82
Table 62. Register 88: STS-1/AU-3 Receive Low-Speed AIS Inhibit Control Bits (R/W) ....................................83
Table 63. Registers 88, 89: STS-1/AU-3 Loss of Signal Detector (R/W) ............................................................83
Table 64. Register 90—95: Continuous N Times Detect (CNTD) Values (R/W) .................................................83
Table 65. Register 95: Continuous N Times Detect (CNTD) B1 Control Bit (R/W) .............................................85
Table 66. Register 96: Test Pattern Drop Control and Status .............................................................................86
Table 67. Register 97: Test Pattern Drop Error Counter (RO) ............................................................................86
Table 68. Register 98: Receive Low-Speed Overhead Control Bits (R/W) .........................................................86
Table 69. Register 99: Receive Low-Speed BIP Error Insert (R/W) ....................................................................87
Table 70. Registers 100—102: Receive Low-Speed Overhead Control Bits (R/W) ............................................87
Table 71. Register 103: Receive Low-Speed L-RDI Inhibit Control (R/W) ..........................................................88
Table 72. Registers 104—106: Receive Low-Speed C1 Byte (R/W) ..................................................................88
Table 73. Registers 107—109: Receive Low-Speed F1 Byte (R/W) ...................................................................88
Table 74. Registers 110—115: Receive Low-Speed K1, K2 Byte Insert (R/W) ..................................................88
Table 75. Registers 116—118: Receive Low-Speed Pass Control (R/W) ...........................................................89
Table 76. Register 127: Page Control Register (R/W) ........................................................................................90
Table 77. Page 0 - Registers 128—191: J1 Insert Parameters (R/W) ................................................................90
Table 78. Page 0 - Registers 192—255: J1 Monitor Bytes (RO) .........................................................................90
Table 79. Page 1 - Registers 128—133: STS-1/AU-3 B1 BIP Error Counters (RO) ...........................................90
Table 80. Page 1 - Registers 134—140: STS-1/AU-3 B2 BIP Error Counters (RO) ...........................................91
Table 81. Page 1 - Registers 141—142: STS-3/STM-1 (AU-4) B1 Error Count (RO) .........................................91
Table 82. Page 1 - Registers 143—145: STS-3/STM-1 (AU-4) B2 Error Count (RO) .........................................91
Table 83. Page 1 - Registers 146—151: STS-3/STM-1 (AU-4) B3 Error Count (RO) .........................................92
Table 84. Page 1 - Registers 152—163: STS-3/STM-1 (AU-4) Pointer Increment/Decrement Counter (RO) ....92
Table 85. Page 1 - Registers 164—166: Receive High-Speed SFEBE Count (RO) ...........................................92
Table 86. Page 1 - Registers 167—172: Receive High-Speed Path FEBE Count (RO) .....................................93
Table 87. Page 2 - Register 131 (R/W) ...............................................................................................................93
Table 88. Page 2 - Registers 128—141 (R/W) ....................................................................................................94
Table 89. Page 2 - Register 145 (R/W) ...............................................................................................................97
Table 90. Page 2 - Registers 142—155 (R/W) ....................................................................................................97
Table 91. Microprocessor Interface I/O Timing Specifications ..........................................................................101
Table 92. Recommended Operating Conditions ...............................................................................................107
Table 93. Power Measurements (VDD = 3.3 V, 23 ×C) ....................................................................................107
Table 94. Logic Interface Characteristics ..........................................................................................................108
Table 95. LVDS Interface Characteristics .........................................................................................................109
Table 96. Input Clock Specifications .................................................................................................................110
Table 97. Input Timing Specifications ................................................................................................................111
Table 98. Output Clock Specifications ...............................................................................................................113
Table 99. Output Timing Specifications .............................................................................................................114
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