參數(shù)資料
型號： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復用器/解復用器
文件頁數(shù)： 39/120頁
文件大?。?/td> 1542K
代理商： TMUX03155
Agere Systems Inc.
39
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions
(continued)
Receive Functions
(continued)
B2 BIP-24 Parity
The device will perform B2 (BIP-24) calculation and error checking. The device will allow access to the B2 errored
bit/block (one block is equal to one frame) count (
BITBLOCKCNT, 0x34,
RHSB2ECNT[16:0], Page 1 - 0x8F—
0x91)
. This counter will update when
LATCH_CNT, 0x04
transitions from a logic 0 to a logic 1.
Signal Degrade BER Algorithm
A signal degrade state and change of state indication will be provided to the control interface (
RHSSD, RHSSDD,
RHSSDM, 0x1B, 0x0A, 0x13
). This bit error rate algorithm can operate on either B1 or B2 errors (
SDB1B2SEL,
0x83
). Signal degrade is declared when
SDLSet[3:0], Page 2 - 0x83
or more bit errors in
SDNsSet[18:0], Page
2 - 0x8E—0x90
and
frames occur
SDMSet[7:0], Page 2 - 0x84
times out of
SDBSet[11:0], Page 2 - 0x85—0x86
blocks (one block is equal to one measurement period of
SDNsSet[18:0]
frames), and it is removed when less
than
SDLClear[3:0], Page 2 - 0x8A
bit errors in
SDNsClear[18:0], Page 2 - 0x87—0x89
frames occur
SDM-
Clear[7:0], Page 2 - 0x8B
times out of
SDBClear[11:0], Page 2 - 0x8C—0x8D
blocks.
The above algorithm can detect bit error rates from 1 x 10
–3
to 1 x 10
–9
.
Signal Fail BER Algorithm
A signal fail state and change of state indication will be provided to the control interface (
RHSSF, RHSSFD,
RHSSFM, 0x1B, 0x0A, 0x13
). This bit error rate algorithm can operate on either B1 or B2 errors (
SFB1B2SEL,
Page 2 - 0x91
). Signal fail is declared when
SFLSet[3:0], Page 2 - 0x91
or more bit errors in
SFNsSet[18:0],
Page 2 - 0x8E—0x90
frames occur
SFMSet[7:0], Page 2 - 0x92
times out of
SFBSet[11:0], Page 2 - 0x93—0x94
blocks (one block is equal to one measurement period of
SFNsSet[18:0]
frames), and it is removed when less than
SFLClear[3:0], Page 2 - 0x98
bit errors in
SFNsClear[18:0], Page 2 - 0x96—0x98
frames occur
SFMClear[7:0]
,
Page 2 - 0x99
times out of
SFBClear[11:0] Page 2 - 0x9A—0x9B
blocks.
The above algorithm can detect bit error rates from 1 x 10
–3
to 1 x 10
–9
.
Section Trace (J0, Z0-2, Z0-3) Byte Monitoring
The device will monitor the section trace bytes (
RJ0MON[7:0]
,
RZ02MON[7:0], RZ03MON[7:0], RCDRLOC,
0x1E, 0x1F, 0x20, 0x1B
) on the receive input. A new section trace value will be detected after
CNTDJ0Z0[3:0],
0x5A
and
consecutive consistent occurrences of a new pattern in the section trace overhead bytes. Any changes
to these bytes will be reported to the control system (
RJ0Z0MOND, RJ0Z0MONM, 0x0C, 0x15
).
Fault Location Monitoring (F1MON)
The device will monitor the fault location byte (
RF1MON0[7:0], 0x21
) on the receive input. A new fault location
state will be detected after
CNTDF1[3:0], 0x5A
consecutive consistent occurrences of a new pattern in the F1
overhead byte. The device will also maintain a history of the previous valid F1 byte (
RF1MON1[7:0], 0x22
). Any
changes to this byte will be reported to the control system (
RF1MOND, RF1MONM, 0x0C, 0x15
).
Automatic Protection Switch (APS) Monitoring
The device will monitor the K1 byte and the K2 byte (5 MSBs only) on the input side of the device receive path
(
RAPSMON[12:0], 0x23, 0x24
). After
CNTDAPS[3:0], 0x5B
consecutive consistent occurrences of new K1 and
K2 bytes, the device will notify the control system (
RAPSMOND, RAPSMONM, 0x0B, 0x14
).
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