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參數(shù)資料
| 型號： | TMUX03155 |
| 英文描述： | TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer |
| 中文描述： | TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器 |
| 文件頁數(shù)： | 5/120頁 |
| 文件大?。?/td> | 1542K |
| 代理商： | TMUX03155 |
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List of Tables
Contents
Page
Agere Systems Inc.
5
Preliminary Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Table 1. Pin Descriptions for the 208-Pin SQFP Package ..................................................................................10
Table 2. Input/Output Summary ..........................................................................................................................15
Table 3. Transmit Mode Control Signals .............................................................................................................16
Table 4. Receive Mode Control ...........................................................................................................................16
Table 5. Input Select Control ...............................................................................................................................17
Table 6. Expected STS-1/AU-3 Input Frame Format ..........................................................................................18
Table 7. STS-3 Output Overhead Format ...........................................................................................................20
Table 8. STM-1 (AU-4) Output Overhead Format ...............................................................................................21
Table 9. STS-1/AU-3 Format and Overhead Control Summary ..........................................................................26
Table 10. STS-1/AU-3 Output Select Control ......................................................................................................27
Table 11. Monitors Disabled During Failure Conditions ......................................................................................28
Table 12. SFEBE Values .....................................................................................................................................33
Table 13. G1 Byte—AU-4 Mode Only .................................................................................................................34
Table 14. PFEBE Values .....................................................................................................................................34
Table 15. Value Offset Load Values ....................................................................................................................36
Table 16. Transport Overhead Byte Access—Transmit Direction .......................................................................36
Table 17. TTOAC Control Bits .............................................................................................................................37
Table 18. STS-1/AU-3 Overhead Control ............................................................................................................42
Table 19. Transport Overhead Byte Access—Receive Direction ........................................................................44
Table 20. Microprocessor Configuration Modes ..................................................................................................47
Table 21. MODE [1—4] Microprocessor Pin Definitions ......................................................................................47
Table 22. Device-Level Register Map .................................................................................................................49
Table 23. Page 0—J1 Byte Insert and Monitor ....................................................................................................51
Table 24. Page 1—Error Counters ......................................................................................................................52
Table 25. Page 2—BER Algorithm Parameters ..................................................................................................53
Table 26. Register 0 (RO) ...................................................................................................................................54
Table 27. Registers 1—3 (RO) ............................................................................................................................54
Table 28. Registers 4, 5: One-Shot Register 0
→
1 (R/W) ..................................................................................54
Table 29. Register 6: Scratch Register (R/W) .....................................................................................................55
Table 30. Registers 7—15: Delta/Event (COR-RO) ............................................................................................55
Table 31. Registers 16—24: Mask Bits (R/W) .....................................................................................................60
Table 32. Registers 25—51: State Bits (RO) .......................................................................................................62
Table 33. Register 52: Mode Control (R/W) ........................................................................................................64
Table 34. Register 53: Low-Speed Transmit Common Signals (R/W) ................................................................65
Table 35. Register 54—59: Transmit Low-Speed Port Input Control (R/W) ........................................................66
Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W) ......................................................67
Table 37. Register 62: Transmit High-Speed Control Signals (R/W) ..................................................................68
Table 38. Register 62, and Page 0, Registers 128—191: Transmit High-Speed J1 Insert (R/W) .......................69
Table 39. Register 62, 69: Transmit High-Speed Control Signals (R/W) ............................................................69
Table 40. Register 62, 66: Transmit High-Speed Control Signals (R/W) ............................................................69
Table 41. Registers 63—65: Trace/Growth Bytes (R/W) .....................................................................................69
Table 42. Register 66: Transmit F1 Data Byte (R/W) ..........................................................................................70
Table 43. Registers 67 and 68: K1 and K2 Insert Bytes (R/W) ...........................................................................70
Table 44. Register 69: Transmit Sync Status Byte (R/W) ...................................................................................70
Table 45. Register 70: Path Signal Trace Byte (R/W) .........................................................................................70
Table 46. Register 71: Path User Channel Byte (R/W) .......................................................................................70
Table 47. Register 72: Path Growth Byte (R/W) ..................................................................................................70
Table 48. Register 73: Tandem Connection Byte (R/W) .....................................................................................71
Table 49. Register 74: Transmit High-Speed Line RDI Insertion Inhibit Bits (R/W) ............................................71
Table 50. Register 75: Transmit High-Speed Path RDI Insertion Inhibit Bits (R/W) ............................................71
Table 51. Register 76: Transmit High-Speed Error Insert Control Parameters (R/W) .........................................72
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