參數(shù)資料
型號: TMUX03155
英文描述: TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述: TMUX03155 STS-3/STM-1(非盟- 4)復(fù)用器/解復(fù)用器
文件頁數(shù): 86/120頁
文件大?。?/td> 1542K
代理商: TMUX03155
86
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 66. Register 96: Test Pattern Drop Control and Status
Table 67. Register 97: Test Pattern Drop Error Counter (RO)
Table 68. Register 98: Receive Low-Speed Overhead Control Bits (R/W)
Address
Dec (Hex)
96 (0x60)
Bit
Name
Function
Reset
Default
1
7
RTSTDRP_OOS
Receive Test Drop Out-of-Sync Indication (RO).
State bit, when at a logic 1, indicates the test pat-
tern is out of sync (OOS); a logic 0 indicates the test
pattern monitor is in sync and able to count bit
errors in the pseudorandom test pattern.
Receive Test Drop Pattern Detect (2
23
– 1) or
(2
15
– 1) (R/W).
Control bit, when set to a logic 0,
causes a Q23 + Q17 + 1 pattern to be monitored;
otherwise, a Q15 + Q14 + 1 pattern is monitored.
Receive Test Drop Port Select Control (R/W).
Control bits specify which TUG-3 the pseudoran-
dom pattern is to be monitored: 00 disable,
01 = TUG-3 #1, 10 = TUG-3 #2, 11 = TUG-3 #3.
96 (0x60)
2
RPAT23or15
0
96 (0x60)
1—0
RTSTDRP_PSEL[1:0]
00
Address
Dec (Hex)
97 (0x61)
Bit
Name
Function
Reset
Default
0x00
7—0
RTSTDRP_ECNT[7:0]
Receive Test Drop Error Count.
Value counts the
number of errors received on the monitored pseu-
dorandom signal. This counter will hold at its maxi-
mum value.
Address
Dec (Hex)
98 (0x62)
Bit
Name
Function
Reset
Default
000
7—5
RA1A2ERRPEN[3—1]
Receive A1A2 Error Insert Port Enables
. Port
into which framing errors will be injected. The num-
ber of consecutive frames that contain errors is con-
trolled by RA1A2ERRINS[4:0] in the same register
in which the action takes place when
RA1A2ERREN, 0x04 transitions from a logic 0 to
logic 1.
RA1A2ERRINS[4:0]
Receive A1A2 Frame Error Insert.
Same as
above.
98 (0x62)
4—0
0x1
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