參數(shù)資料
型號： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復用器/解復用器
文件頁數(shù)： 12/120頁
文件大小： 1542K
代理商： TMUX03155
12
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Pin Information
(continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package
(continued)
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.
I = input, O = output, I/O = bidirectional signal, I
d
= input with internal pull-down (~20 kW), I
u
= input with internal pull-up (~100 kW), I
diff
or
O
diff
= differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or out-
puts. LVDS = low-voltage differential signal.
Pin
*
Symbol
Type
Name/Description
Receive Direction Signals
Receive High-Speed Serial Clock Input.
The STS-3/STM-1
(AU-4) serial clock is 155.52 MHz.
Center Tap for Receive High-Speed Serial Clock Input.
The cen-
ter tap input provides for center-tapped common-mode termination.
This input should be terminated through an external capacitor to
ground (approximately 0.1 μF).
Receive High-Speed Serial Data Input.
The STS-3/STM-1 (AU-4)
serial data is 155.52 Mbits/s.
Center Tap for Receive High-Speed Serial Data Input.
The center
tap input provides for center-tapped common-mode termination. This
input should be terminated through an external capacitor to ground
(approximately 0.1 μF).
Receive CDR Bias Resistor Input.
Must be tied to ground, through
an external 10 k
±1% resistor.
Receive High-Speed Clock Input.
The STS-3/STM-1 (AU-4) clock
is 38.88 MHz (nibble), or 19.44 MHz for byte-wide data.
Receive High-Speed Data Inputs.
Data bit 7 is the most significant
bit in nibble or byte mode.
Receive High-Speed Input Parity.
The parity input is only defined
for nibble- or byte-wide data. The device can be provisioned to
accept either odd or even parity.
Receive High-Speed Loss of Signal
. This is an active-high signal.
Receive STS-1/AU-3 Output Clock
. The STS-1/AU-3 clock will be
19.44 MHz for byte-wide data (bus mode).
Receive STS1/AU-3 Output J0 Time
. This signal will be active
(logic 1) each time the J0 byte is output.
Receive STS-1/AU-3 Output Data
. RLSDATA7O is the most signifi-
cant bit of the output byte.
124, 123
RHSSCLKIT/C
I
diff
LVDS
I
122
CTAP_RHSSCLKI
119, 118
RHSSDATAIT/C
I
diff
LVDS
I
117
CTAP_RHSSDATAI
113
RCDR10K2GND
I
50
RHSCLKI
I
d
56—63
RHSDATA[7:0]I
I
d
55
RHSPARI
I
u
49
179
RHSLOSEXTI
RLSCLKO
I
d
O
176
RLSJ0TIMEO
O
181,
183—186,
188—190
192
RLSDATA[7:0]O
O
RLSPARO
O
Receive STS-1/AU-3 Output Parity.
The device can be provisioned
to source either an odd or even parity bit per byte transfer.
STS-3/STM-1 (AU-4) Transport Overhead Access Channel (TOAC) Drop
RTOACCLKO
O
Receive TOAC Clock.
(5.184 MHz.)
RTOACSYNCO
O
Receive TOAC Sync.
(8 kHz.)
RTOACDATAO
O
Receive TOAC Data.
(5.184 Mbits/s.)
41
42
43
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