參數(shù)資料
型號: TMUX03155
英文描述: TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述: TMUX03155 STS-3/STM-1(非盟- 4)復(fù)用器/解復(fù)用器
文件頁數(shù): 14/120頁
文件大小: 1542K
代理商: TMUX03155
14
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Pin Information
(continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package
(continued)
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.
I = input, O = output, I/O = bidirectional signal, I
d
= input with internal pull-down (~20 kW), I
u
= input with internal pull-up (~100 kW), I
diff
or
O
diff
= differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or out-
puts. LVDS = low-voltage differential signal.
Pin
*
Symbol
Type
Name/Description
Microprocessor Interface
(continued)
I
u
Chip Select (Active-Low).
This pin is asserted low by the micropro-
cessor to enable the microprocessor interface. If MPMUX = 1, an
internal 100 k
pull-up is on this pin.
O
Interrupt.
This pin is asserted high to indicate an interrupt produced
by an alarm condition. The activation of this pin can be masked by
the microprocessor by setting the appropriate mask bits.
O
Ready.
If MPMODE = 1, this pin is asserted high to indicate the
device has completed a read or write operation. This pin is in a high-
impedance state when CS is high.
Data Transfer Acknowledge (Active-Low).
If MPMODE = 0, this
pin is asserted low to indicate the device has completed a read or
write operation.
I/O
Microprocessor Interface Address/Data Bus.
If MPMUX = 0,
these pins become the bidirectional, 3-state data bus. If MPMUX = 1,
these pins become the multiplexed address/data bus.
I
d
Microprocessor Interface Address.
If MPMUX = 0, these pins
become the address bus for the microprocessor interface registers.
JTAG Signals
I
u
JTAG Clock.
I
u
JTAG Input Data.
I
u
JTAG Mode Select.
I
u
JTAG Reset (Active-Low).
O
JTAG Output Data.
SCAN Specific Inputs
I
u
Scan Enable.
Place device in scan mode (active-low).
I
d
Test Mode.
Disable all clocks and async resets (active-high).
O
CDR Test Output.
Test purpose only.
LVDS Control Signals
I
u
LVDS Reference Select.
If LVDS_REFSEL = 0, then use external
1.0 and 1.4 reference voltages. If LVDS_REFSEL = 1, then use inter-
nal references.
I
1.0 V Reference for LVDS Buffers.
This signal is
optional.
I
1.4 V Reference for LVDS Buffers.
This signal is
optional.
I
LVDS Resistor Pins.
A 100
±1% resistor must be placed between
these two pins when using the LVDS buffers.
I
7
CS
8
INT
13
RDY_DTACK
5—3,
206—202
AD[7:0]
201—197,
195—193
A[7:0]
20
22
23
24
25
TCLK
TDI
TMS
TRST
TDO
27
28
114
SCAN_EN
TEST_MODE
CDR_TSTMUX0
146
LVDS_REFSEL
129
128
127
126
LVDS_REF10
LVDS_REF14
LVDS_RESHI
LVDS_RESLO
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