參數(shù)資料
型號(hào): TMUX03155
英文描述: TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述: TMUX03155 STS-3/STM-1(非盟- 4)復(fù)用器/解復(fù)用器
文件頁(yè)數(shù): 67/120頁(yè)
文件大?。?/td> 1542K
代理商: TMUX03155
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Agere Systems Inc.
67
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W)
Address
Dec (Hex)
60 (0x3C)
Bit
Name
Function
Reset
Default
0
7
THSCLKSEL_DorS
Transmit High-Speed Clock Select Differential
or Single-Ended Inputs.
Control bit, when set to a
logic 0, selects the differential clock and sync inputs
(THSSCLKIT/C (pins 143, 142), THSSJ0J1V1IT/C
(pins 140, 139)) for driving the transmit direction of
the device; otherwise, the single-ended inputs
(THSCLKI, THSJ0J1V1I) are selected.
Transmit High-Speed Parity Odd or Even Gener-
ation.
Control bit, when set to a logic 0, causes odd
parity to be inserted in nibble/parallel mode per
clock transfer on the STS-3/STM-1 (AU-4) output; a
logic 1 causes even parity to be generated.
Transmit High-Speed A1 or End Sync Align-
ment.
Control bit, when set to a logic 0, causes the
output sync to be coincident with the first bit, nibble,
or byte of the outgoing frame; a logic 1 causes the
sync to be coincident with the last bit, nibble, or byte
of the frame.
Transmit High-Speed Clock Invert.
Control bit,
when set to a logic 1, causes the output clock to be
inverted, a logic 0 doesn’t effect the clock.
Transmit High-Speed Port Type.
Control bits con-
trol the type of output port (STS-3/STM-1 (AU-4):
00 = serial, 01 = nibble, 10 = byte mode).
Transmit High-Speed Clock Type.
Control bits
control the type of transmit clock being provided to
the device: 00 = serial clock (155.52 MHz), 01 =
nibble clock (38.88 MHz), 10 = byte clock (19.44
MHz).
60 (0x3C)
6
THSPAROEG
0
60 (0x3C)
5
THSSA1orEnd
0
60 (0x3C)
4
THSCLKINV
0
60 (0x3C)
3—2
THSPTYPE[1:0]
00
60 (0x3C)
1—0
THSCLKTYPE[1:0]
00
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