參數(shù)資料
型號： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復用器/解復用器
文件頁數(shù)： 54/120頁
文件大?。?/td> 1542K
代理商： TMUX03155
54
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Description
This section gives a brief description of each register bit and its functionality. All algorithms are described in the
main text of the document or in the maintenance section of the document. The abbreviations after each register
indicate if the register is read only (RO), clear-on-read (COR), or read/write (R/W).
Table 26. Register 0 (RO)
Table 27. Registers 1—3 (RO)
Table 28. Registers 4, 5: One-Shot Register 0
→
1 (R/W)
Address
Dec (Hex)
0 (0x00)
Bit
Name
Function
Reset
Default
0
0
INT
Interrupt.
The
active-high
bit is a copy of the INT
pin. This bit is the ORing of all event and delta bits
(registers 0x07—0x0F). An event or delta bit
contribution can be inhibited from contributing to
this bit by setting the appropriate mask bit (see
Mask Bit Operation on page 28).
Address
Dec (Hex)
1 (0x01)
Bit
Name
Function
Reset
Default
0x31
7—0
DEVID[15:8]
Device ID.
Upper device ID byte of the number
which uniquely identifies the device.
Device ID.
Lower device ID byte of the number
which uniquely identifies the device.
Device Version Number.
Device version register
will change each time the device is changed.
2 (0x02)
7—0
DEVID[7:0]
0x55
3 (0x03)
7—0
DEVVER[7:0]
0x03
Address
Dec (Hex)
4 (0x04)
Bit
Name
Function
Reset
Default
0
7
TA1A2ERREN
Transmit A1/A2 Error Enable.
Inserts framing
errors into the output STS-3/STM-1 (AU-4) signal.
The number of consecutive errors is controlled by
TA1A2ERRINS[4:0], 0x4D.
Test Generation 8 Error Insert.
Inserts eight errors
into the pseudorandom signal being inserted into
the selected TUG-3 signal.
Signal Fail Clear.
Allows the signal fail algorithm to
be forced into the normal state.
Signal Fail Set.
Allows the signal fail algorithm to
be forced into the failed state.
Signal Degrade Clear.
Allows the signal degrade
algorithm to be forced into the normal state.
Signal Degrade Set.
Allows the signal degrade
algorithm to be forced into the failed state.
4 (0x04)
6
TSTGENE8INS
0
4 (0x04)
5
SFCLEAR
0
4 (0x04)
4
SFSET
0
4 (0x04)
3
SDCLEAR
0
4 (0x04)
2
SDSET
0
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