參數(shù)資料
型號： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器
文件頁數(shù)： 81/120頁
文件大?。?/td> 1542K
代理商： TMUX03155
Agere Systems Inc.
81
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 59. Register 85: Receive High/Low-Speed Port Control (R/W)
Address
Dec (Hex)
85 (0x55)
Bit
Name
Function
Reset
Default
0
7
THS2RHSLB
Transmit High-Speed Receive High-Speed
Loopback Control.
Control bit, when set to a logic
1, causes the transmit output STS-3/STM-1 (AU-4)
signal to be looped back to the receive input; other-
wise, the loopback is disabled.
Receive High-Speed Descramble Enable.
Control
bit, when set to a logic 1, causes the input STS-3/
STM-1 (AU-4) signal to be descrambled; otherwise,
the signal is not descrambled.
Receive Concatenation Mode.
Control bit, when
set to a logic 1, causes the input pointer interpreter
to operate in concatenation mode. This mode is
most likely used in the AU-4 mode; otherwise, three
independent pointers are expected.
Receive RDI Monitor Path Yellow or Enhanced
Failure Code.
Control bit, when set to a logic 0,
causes the device to monitor path yellow in the
incoming G1 byte bit 3; otherwise, the device moni-
tors for an enhanced failure code in the G1 byte bits
3 down to 1.
Receive High-Speed Verify Odd or Even Parity.
Control bit when, set to a logic 0, causes odd parity
to be verified in nibble/parallel mode per clock
transfer on the STS-3/STM-1 (AU-4) input; other-
wise, even parity is verified.
Receive High-Speed Retime Edge Control.
Con-
trol bit, when set to a logic 1, causes the STS-3/
STM-1 (AU-4) input data to be retimed on the posi-
tive edge; otherwise, the input STS-3/STM-1 (AU-4)
input data is retimed on the falling edge of the input
clock.
Receive High-Speed Port Type.
Control bits are
used to control the type of output interface required:
00 = serial interface, 01 = nibble interface,
10 = byte-wide interface.
85 (0x55)
6
RHSDSCR
0
85 (0x55)
5
RCONCATMODE
0
85 (0x55)
4
RRDI_MPYorEFC
0
85 (0x55)
3
RHSVOEPAR
0
85 (0x55)
2
RHSEDGE
0
85 (0x55)
1—0
RHSPTYPE[1:0]
00
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