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| 型號(hào)： | TMUX03155 |
| 英文描述： | TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer |
| 中文描述： | TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器 |
| 文件頁(yè)數(shù)： | 23/120頁(yè) |
| 文件大?。?/td> | 1542K |
| 代理商： | TMUX03155 |
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Agere Systems Inc.
23
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Transmit Direction Overview
(continued)
Transport Overhead Access Channel (TOAC) Insert
The device will allow the insertion of overhead data from the transmit TOAC under user control. (See TTOAC in the
Maintenance Functions section, page 36, for more details.)
STS-3/STM-1 (AU-4) Scramble Enable
Scrambling of the STS-3/ STM-1 (AU-4) signal is provisionable (
THSSCR, 0x3D
). A frame synchronous scram-
bling sequence 1 + x
6
+ x
7
is used. The sequence is reset to 1111111 at the beginning of the byte following the Z0-
3 byte and scrambles all of the STS-3/STM-1 (AU-4) data except all the A1, A2 and J0, Z0 bytes. Writing a logic 1
to this bit causes the signal to be scrambled.
STS-3/STM-1 (AU-4) B1, B2, and B3 BIP Generation
The device will generate a B1-BIP-8, B2-BIP-24, and a B3-BIP-8 (AU-4 mode only) on the output signal. Each BIP
calculator can be programmed to insert an inverted BIP value (
THSB1ERRINS
,
THSB2ERRINS[3—1]
,
THSB3ERRINS, 0x4C
).
STS-3/STM-1 (AU-4) Loopback Control
The output STS-3/STM-1 (AU-4) signal can be replaced by the receive STS-3/STM-1 (AU-4) signal under software
control (
RHS2THSLB, 0x3D
). The output format (bit, nibble, or byte) will be the same as the receive input format
not the transmit output port format.
Note:
The transmit port type must be programmed to be the same as the receive input type.
STS-3/STM-1 (AU-4) Output Interface
The transmit STS-3/STM-1 (AU-4) output can either be serial at 155.52 Mbits/s, nibble at 38.88 Mbits/s, or byte at
19.44 Mbits/s. This is controlled by writing to
THSPTYPE[1:0], 0x3C
. The data is clocked out of the device on the
rising edge of the clock. This clock can be inverted leaving the device (
THSCLKINV, 0x3C
). When provisioned in
the parallel or nibble mode, an even or odd parity bit is generated per transfer (
THSPAROEG, 0x3C
). The output
sync can be programmed to be active on the first clock cycle of the frame (A1-1 coincident with sync) or the last
clock cycle of the frame (
THSSA1orEND, 0x3C
).
The output clock, sync, and data signals can be placed in a high-impedance state under user control (
THSCHIZ
=
1,
THSSHIZ
= 1,
THSDHIZ
= 1,
0x3D
). Unused outputs in serial and nibble mode will be placed in a high-
impedance state automatically by the device.
The following functions are performed in the receive direction: input retime, clock and data recovery, STS-3/STM-1
(AU-4) framing, loss-of-signal detection, loopback select logic, RSTS-3/STM-1 (AU-4) frame synchronous
descrambling, TOAC drop, B1, B2, and B3 checking, monitoring functions, pointer interpretation, data demultiplex
and conversion (AU-4 mode only), STS-1/AU-3 output byte control, B1 and B2 generate, STS-1/AU-3 output
scramble, output selection logic, and output data formatter.
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