參數(shù)資料
型號(hào): TMUX03155
英文描述: TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述: TMUX03155 STS-3/STM-1(非盟- 4)復(fù)用器/解復(fù)用器
文件頁(yè)數(shù): 13/120頁(yè)
文件大?。?/td> 1542K
代理商: TMUX03155
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Agere Systems Inc.
13
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Pin Information
(continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package
(continued)
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.
I = input, O = output, I/O = bidirectional signal, I
d
= input with internal pull-down (~20 kW), I
u
= input with internal pull-up (~100 kW), I
diff
or
O
diff
= differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or out-
puts. LVDS = low-voltage differential signal.
Pin
*
Symbol
Type
Name/Description
Mode/In-Circuit Test and Reset Control Inputs
I
u
In-Circuit Test Control (Active-Low).
If
ICT
is forced low, certain
output pins are placed in the high-impedance state.
I
u
Hardware Reset (Active-Low).
If
RESET
is forced low, all internal
states in the transceiver paths are reset and data flow through each
channel will be interrupted.
I
u
Test Reset (Active-Low)
. This pin is for test purposes only; it should
be left unconnected.
I
u
, I
d
Mode Control
. Normal STS-3/STM-1 mode set MODE [1:0] = 10.
STS-1 mode set MODE [1:0] = 00
Microprocessor Interface
I
Microprocessor Multiplex Mode.
Setting MPMUX = 1 allows the
microprocessor interface to accept the multiplexed address and data
signals. Setting MPMUX = 0 allows the microprocessor interface to
accept demultiplexed (separate) address and data signals.
I
Microprocessor Mode.
When MPMODE = 1, the device uses the
address latch enable type microprocessor read/write protocol with
separate read and write controls. Setting MPMODE = 0 allows the
device to use the address strobe type microprocessor read/write pro-
tocol with a separate data strobe and a combined read/write control.
MPMODE3ALE
I
u
Microprocessor MODE3 ALE Enable.
When the device is in
MODE3 (MPMODE = 1 and MPMUX = 0), the ALE signal can be
used to retime the address or the address bus can be used directly
without being retimed. This is an active-high signal.
I
Write (Active-Low).
If MPMODE = 1, this pin is asserted low by the
microprocessor to initiate a write cycle.
Data Strobe (Active-Low).
If MPMODE = 0, this pin becomes the
data strobe for the microprocessor. When R/
W
= 0 (write), a low
applied to this pin latches the signal on the data bus into internal reg-
isters.
I
Address Latch Enable.
If MPMODE = 1, this pin becomes the
address latch enable for the microprocessor. When this pin transi-
tions from high to low, the address bus inputs are latched into the
internal registers.
Address Strobe (Active-Low).
If MPMODE = 0, this pin becomes
the address strobe for the microprocessor. When this pin transitions
from high to low, the address bus inputs are latched into the internal
registers.
I
Read (Active-Low).
If MPMODE = 1, this pin is asserted low by the
microprocessor to initiate a read cycle.
Read/Write.
If MPMODE = 0, this pin is asserted high by the micro-
processor to indicate a read cycle or asserted low to indicate a write
cycle.
30
ICT
106
RESET
111
RSTN_TST
153, 154
MODE [1:0]
14
MPMUX
15
MPMODE
16
9
WR_DS
11
ALE_AS
10
RD_R/W
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