參數(shù)資料
型號: TMUX03155
英文描述: TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述: TMUX03155 STS-3/STM-1(非盟- 4)復(fù)用器/解復(fù)用器
文件頁數(shù): 64/120頁
文件大?。?/td> 1542K
代理商: TMUX03155
64
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 32. Registers 25—51: State Bits (RO)
(continued)
Table 33. Register 52: Mode Control (R/W)
Address
Dec (Hex)
35 (0x23)
36 (0x24)
37 (0x25)
Bit
Name
Function
Reset
Default
0000000
000000
0x00
7—3
7—0
7—0
RAPSMON[12:8]
RAPSMON[7:0]
RS1MON[7:0]
Receive APS Monitor Value.
See (addr 0x0B) for
description.
Receive S1 Monitor Value.
See (addr 0x0C) for
description.
Receive C2 Monitor Path Values.
See (addr
0x0D) for description.
38 (0x26)
39 (0x27)
40 (0x28)
41 (0x29)
42 (0x2A)
43 (0x2B)
44 (0x2C)
45 (0x2D)
46 (0x2E)
47 (0x2F)
48 (0x30)
49 (0x31)
50 (0x32)
50 (0x32)
51 (0x33)
7—0
RC2MON[1—3][7:0]
0x00
7—0
RF2MON[1—3][7:0]
Receive F2 Monitor Path Values.
See (addr 0x0E)
for description.
0x00
7—0
RZ3MON[1—3][7:0]
Receive Z3 Monitor Path Values.
See (addr 0x0E)
for description.
0x00
7—0
RZ5MON[1—3][7:0]
Receive Z5 Monitor Path Values.
See (addr 0x0F)
for description.
0x00
5—3
2—0
2—0
RRDIP2[2:0]
RRDIP1[2:0]
RRDIP3[2:0]
Receive RDI-P Monitor Path Values (G1 Byte).
See (addr 0x0D) for description.
000
Address
Dec (Hex)
52 (0x34)
Bit
Name
Function
Reset
Default
0
7
RSONET_SDH
Receive SONET or SDH Mode.
Control bit, when
set to a logic 0, puts the device receive path into the
SONET mode
;
otherwise,
the device receive path
remains in
SDH mode. For STS-1 mode, set both
RSONET_SDH and RSTS3_AU4 to a logic 0, and
tie the external mode control pins low.
Receive STS3 or AU4 Mode.
Control bit, when set
to a logic 0, puts
the device receive path into the
STS-3 mode (three STS-1 signals multiplexed into
an STS-3 signal); otherwise, AU-4 mode (three AU-
3 signals multiplexed into an STM-1 (AU-4) signal).
For STS-1 mode, set both RSONET_SDH and
RSTS3_AU4 to a logic 0, and tie the external mode
control pins low.
Mode Value from External Pins (RO).
Read-only
status bits allow monitoring of the external mode
control pins.
52 (0x34)
6
RSTS3_AU4
0
52 (0x34)
5—4
MODE [1:0]
Must be
set to 10.
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