參數(shù)資料
型號: TMUX03155
英文描述: TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述: TMUX03155 STS-3/STM-1(非盟- 4)復用器/解復用器
文件頁數(shù): 92/120頁
文件大?。?/td> 1542K
代理商: TMUX03155
92
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 83. Page 1 - Registers 146—151: STS-3/STM-1 (AU-4) B3 Error Count (RO)
Table 84. Page 1 - Registers 152—163: STS-3/STM-1 (AU-4) Pointer Increment/Decrement Counter (RO)
Table 85. Page 1 - Registers 164—166: Receive High-Speed SFEBE Count (RO)
Address
Dec (Hex)
146 (0x92)—
151 (0x97)
Bit
Name
Function
Reset
Default
0x0000
7—0
RHSB3ECNT[1—3][15:8]
RHSB3ECNT[1—3][7:0]
Receive High-Speed B3 Error Count.
Counts
the number of B3 errors in the receive STS-3/
STM-1 (AU-4) frame. Only counter value 1 is valid
in AU-4 mode. This counter can either count
actual BIP errors or block errors (BITBLOCKCNT,
0x34). This counter holds at its maximum value
and transfers its internal count to a holding regis-
ter when LATCH_CNT, 0x04
transitions from a
logic 0 to 1.
Address
Dec (Hex)
152 (0x98)
153 (0x99)
154 (0x9A)
155 (0x9B)
156 (0x9C)
157 (0x9D)
158 (0x9E)
159 (0x9F)
160 (0xA0)
161 (0xA1)
162 (0xA2)
163 (0xA3)
Bit
Name
Function
Reset
Default
0x000
2—0
7—0
2—0
7—0
2—0
7—0
2—0
7—0
2—0
7—0
2—0
7—0
RPTR_INC1[10:8]
RPTR_INC1[7:0]
RPTR_INC2[10:8]
RPTR_INC2[7:0]
RPTR_INC3[10:8]
RPTR_INC3[7:0]
RPTR_DEC1[10:8]
RPTR_DEC1[7:0]
RPTR_DEC2[10:8]
RPTR_DEC2[7:0]
RPTR_DEC3[10:8]
RPTR_DEC3[7:0]
Receive Pointer Increment Count.
Counts the
number of increments in the incoming pointer val-
ues. This counter holds at its maximum value and
transfers its internal count to a holding register
when LATCH_CNT, 0x04
transitions from a logic
0 to 1.
Receive Pointer Decrement Count.
Counts the
number of decrements in the incoming pointer
values. This counter holds at its maximum value
and transfers its internal count to a holding regis-
ter when LATCH_CNT, 0x04
transitions from a
logic 0 to 1.
0x000
Address
Dec (Hex)
164 (0xA4)
165 (0xA5)
166 (0xA6)
Bit
Name
Function
Reset
Default
0x00000
1—0
7—0
7—0
RSFEBECNT[17:16]
RSFEBECNT[15:8]
RSFEBECNT[7:0]
Receive Section FEBE Count.
Counts the num-
ber of B2 errors received in the M1 byte of the
receive STS-3/STM-1 (AU-4) frame. This counter
can either count actual SFEBE errors or block
errors (FEBEBITBLOCKCNT, 0x34). This counter
holds at its maximum value and transfers its inter-
nal count to a holding register when LATCH_CNT,
0x04 transitions from a logic 0 to 1.
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