參數(shù)資料
型號: TMUX03155
英文描述: TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述: TMUX03155 STS-3/STM-1(非盟- 4)復用器/解復用器
文件頁數(shù): 101/120頁
文件大?。?/td> 1542K
代理商: TMUX03155
Agere Systems Inc.
101
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
I/O Timing
The I/O timing specifications for the microprocessor interface are given in Table 92. The microprocessor interface
pins use CMOS I/O levels. All outputs, except the address/data bus AD[7:0], are rated for a capacitive load of
50 pF. The AD[7:0] outputs are rated for a 100 pF load. The minimum read and write cycle time is 200 ns for all
device configurations.
The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 7—14.
Table 91. Microprocessor Interface I/O Timing Specifications
Symbol
Configuration
Parameter
Setup
(ns)
(Min)
Hold
(ns)
(Min)
Delay
(ns)
(Max)
t1
MODES 1 and 2
Address Valid to
AS
Asserted (Read, Write)
5
t2
AS
Asserted to Address Invalid (Read, Write)
10
t3
AS
Asserted to
DS
Asserted
0
t4
R/
W
High (Read) to
DS
Asserted
25
t5
DS
Asserted (Read, Write) to
DTACK
Asserted
20
t6
DTACK
Asserted to Data Valid (Read)
24
t7
DS
Asserted (Read) to Data Valid
44
t8
DS
Negated (Read, Write) to
AS
Negated
t9
DS
Negated (Read) to Data Invalid
15
t10
DS
Negated (Read) to
DTACK
Negated
15
t11
AS
(Read, Write) Asserted Width
55
t12
DS
(Read) Asserted Width
25
t13
AS
Asserted to R/
W
Low (Write)
7
t14
R/
W
Low (Write) to
DS
Asserted
20
t15
Data Valid to
DS
Asserted (Write)
7.5
t16
DS
Negated to
DTACK
Negated (Write)
20
t17
DS
Negated to Data Invalid (Write)
7.5
t18
DS
(Write) Asserted Width
30
t19
MODES 3 and 4
Address Valid to ALE Asserted Low (Read, Write)
15
t20
ALE Asserted Low (Read, Write) to Address Invalid
10
t21
ALE Asserted Low to
RD
Asserted (Read)
30
t22
RD
Asserted (Read) to Data Valid
90
t23
RD
Asserted (Read) to RDY Asserted
75
t24
RD
Negated to Data Invalid (Read)
15
t25
RD
Negated to RDY Negated (Read)
25
t26
ALE Asserted Low to
WR
Asserted (Write)
35
t27
CS
Asserted to RDY Asserted Low
16
t28
Data Valid to
WR
Asserted (Write)
25
t29
WR
Asserted (Write) to RDY Asserted
73
t30
WR
Negated to RDY Negated (Write)
22
t31
WR
Negated to Data Invalid
25
t32
ALE Asserted (Read, Write) Width
150
t33
RD
Asserted (Read) Width
100
t34
WR
Asserted (Write) Width
100
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