參數(shù)資料
型號： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器
文件頁數(shù)： 62/120頁
文件大?。?/td> 1542K
代理商： TMUX03155
62
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 31. Registers 16—24: Mask Bits (R/W)
(continued)
Table 32. Registers 25—51: State Bits (RO)
Address
Dec (Hex)
22 (0x16)
Bit
Name
Function
Reset
Default
0
7
RHSNPIMISM
Receive High-Speed NPI Mismatch Mask.
See
(addr 0x0D) for description.
Receive High-Speed H4 Mismatch Mask.
See
(addr 0x0D) for description.
Receive RDI-P Mask.
See (addr 0x0D) for descrip-
tion.
Receive C2 Monitor Mask.
See (addr 0x0D) for
description.
Receive Z3 Monitor Mask.
See (addr 0x0E) for
description.
Receive F2 Monitor Mask.
See (addr 0x0E) for
description.
Receive Z5 Monitor Mask.
See (addr 0x0F) for
description.
22 (0x16)
6
RHSH4MISM
0
22 (0x16)
5—3
RRDIPM[3—1]
000
22 (0x16)
2—0
RC2MONM[3—1]
000
23 (0x17)
5—3
RZ3MONM[3—1]
000
23 (0x17)
2—0
RF2MONM[3—1]
000
24 (0x18)
2—0
RZ5MONM[3—1]
000
Address
Dec (Hex)
25 (0x19)
Bit
Name
Function
Reset
Default
Unde-
fined.
Unde-
fined.
7
TILOC
Transmit Input Loss-of-Clock (State).
See (addr
0x07) for description.
Transmit Input Loss-of-Frame (State).
See (addr
0x07) for description.
25 (0x19)
6
TILOF
Note:
This feature is not supported in version 3 of
the device.
Transmit Low-Speed Loss-of-Frame (State).
See
(addr 0x08) for description.
Transmit Low-Speed Out-of-Frame (State).
See
(addr 0x08) for description.
Transmit RDI-P Internal (State).
State bit indicates
when Path RDI is active. (Valid only in AU-4 mode.)
Transmit RDI-L Internal (State).
State bit indicates
when Line RDI is active.
Transmit Low-Speed H4 Mismatch (State).
See
(addr 0x09) for description.
Transmit Low-Speed Pointer Mismatch (State).
See (addr 0x09) for description.
Receive Clock Data Recovery Loss-of-Clock
(State).
State bit indicates when the internal CDR
clock is missing. This is an active-high signal.
Receive High-Speed Signal Fail (State).
See
(addr 0x0A) for description.
Receive High-Speed Signal Degrade (State).
See
(addr 0x0A) for description.
25 (0x19)
5—3
TLSLOF[3—1]
111
25 (0x19)
2—0
TLSLOOF[3—1]
111
26 (0x1A)
7
TPRDIINT
1
26 (0x1A)
6
TLRDIINT
1
26 (0x1A)
5—3
TLSH4MIS[3—1]
000
26 (0x1A)
2—0
TLSPTRMIS[3—1]
000
27 (0x1B)
7
RCDRLOC
Unde-
fined.
27 (0x1B)
6
RHSSF
1
27 (0x1B)
5
RHSSD
1
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