參數(shù)資料
型號： TMUX03155
英文描述： TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
中文描述： TMUX03155 STS-3/STM-1（非盟- 4）復(fù)用器/解復(fù)用器
文件頁數(shù)： 68/120頁
文件大?。?/td> 1542K
代理商： TMUX03155
68
Agere Systems Inc.
Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
(continued)
Register Map
(continued)
Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W)
(continued)
Table 37. Register 62: Transmit High-Speed Control Signals (R/W)
Address
Dec (Hex)
61 (0x3D)
Bit
Name
Function
Reset
Default
0
7
THSSCR
Transmit High-Speed Scramble Enable.
Control
bit, when set to a logic 1, causes the output STS-3/
STM-1 (AU-4) signal to be scrambled; the signal is
not scrambled if set to a logic 0.
Receive High-Speed to Transmit High-Speed
Loopback Control.
Control bit, when set to a logic
1, causes the receive STS-3/STM-1 (AU-4) input
signal to be looped back to the transmit high-speed
output; loopback is disabled when set to a logic 0.
Transmit High-Speed Clock High-Impedance
(Control).
Control signal, when set to a logic 1,
causes the output STS-3/STM-1 (AU-4) clock to be
placed in a high-impedance state; a logic 0 enables
the output driver.
Transmit High-Speed Sync High-Impedance
(Control).
Control signal, when set to a logic 1,
causes the output STS-3/STM-1 (AU-4) sync signal
to be placed in a high-impedance state; a logic 0
enables the output driver.
Transmit High-Speed Data High-Impedance
(Control).
Control signal, when set to a logic 1,
causes the output STS-3/STM-1 (AU-4) data sig-
nals to be placed in a high-impedance state; a logic
0 enables the output drivers.
61 (0x3D)
6
RHS2THSLB
0
61 (0x3D)
2
THSCHIZ
0
61 (0x3D)
1
THSSHIZ
0
61 (0x3D)
0
THSDHIZ
0
Address
Dec (Hex)
62 (0x3E)
Bit
Name
Function
Reset
Default
00
7—6
TSS[1:0]
Transmit SS (Bits).
These bits are used in the
STS-1 mode to set the SS bits when an unequipped
signal is being generated.
Transmit Path FEBE Inhibit.
Control bit, when set
to a logic 1, disables hardware insertion of Path
FEBE (B3 errors) in the outgoing STM-1 (AU-4)
frame G1 byte; a logic 0 enables hardware insertion
of PFEBE. Only valid in AU-4 mode.
Transmit Section FEBE Inhibit.
Control bit, when
set to a logic 1, disables hardware insertion of Sec-
tion FEBE (B2 errors) in the outgoing STS-3/STM-1
frame M1 byte; a logic 0 enables hardware insertion
of SFEBE.
62 (0x3E)
4
TPFEBEINH
0
62 (0x3E)
3
TSFEBEINH
0
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