
82371AB (PIIX4)
E
112
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Bit
Description
2
Resume Detect.
The Host Controller sets this bit to 1 when it receives a “RESUME” signal from
a USB device. This is only valid if the Host Controller is in a global suspend state (bit 3 of Command
register=1).
1
USB Error Interrupt.
The Host Controller sets this bit to 1 when completion of a USB transaction
results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt
occurred also had its IOC bit set, both this bit and bit 0 are set.
0
USB Interrupt (USBINT).
The Host Controller sets this bit to 1 when the cause of an interrupt is a
completion of a USB transaction whose Transfer Descriptor had its IOC bit set.
The Host Controller also sets this bit to 1 when a short packet is detected (actual length field in TD is
less than maximum length field in TD), and short packet detection is enabled in that TD.
6.2.3.
USBINTR—USB INTERRUPT ENABLE REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (04
05h)
0000h
Read/Write
This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and
the corresponding interrupt is active, an interrupt is generated to the host. Fatal errors (Host Controller
Processor Error bit 4, USBSTS Register) cannot be disabled by the host controller. Interrupt sources that are
disabled in this register still appear in the Status Register to allow the software to poll for events.
Bit
Description
15:4
Reserved
.
3
Short Packet Interrupt Enable.
1=Enabled. 0=Disabled.
2
Interrupt On Complete (IOC) Enable.
1=Enabled. 0=Disabled.
1
Resume Interrupt Enable.
1=Enabled. 0=Disabled.
0
Time-out/CRC Interrupt Enable.
1=Enabled. 0=Disabled.