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參數(shù)資料
| 型號： | FW82371 |
| 廠商： | Intel Corp. |
| 英文描述： | PCI-TO-ISA / IDE XCELERATOR PIIX4 |
| 中文描述： | PCI到的ISA / IDE的XCELERATOR PIIX4 |
| 文件頁數(shù)： | 205/284頁 |
| 文件大?。?/td> | 1042K |
| 代理商： | FW82371 |
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synthesizer. The Host clocks stop running in this state. The processor does not snoop host bus cycles and
system designers must ensure that no host cycles to main memory are executed by other system masters. To
exit this state, PIIX4 negates the CPU_STP# signal. Again, PIIX4 loads the Fast Burst Timer with the
[CPU_LCK] value and count down allowing time for the processor PLL to lock. After the timer expires, PIIX4
negates
the
SUS_STAT1#
signal,
the
(if applicable), and STP_CLK#.
82371AB (PIIX4)
205
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
SLP#
signal,
and
ZZ
signal
System Throttle Control:
If the system has been placed into the Stop Grant or Quick Start states and
[THT_EN] bit is set, PIIX4 toggles the STPCLK# signal and ZZ signal (if [ZZ_EN] set) with a period of 244
μ
s
(approximately eight 32-kHz clock periods) and a programmable duty cycle. This system toggles between full-
speed operation and the Stop Grant or Quick Start state. The duty cycle can be set in 12.5% increments by
programming the [THTL_DTY] bits in the Processor Control (P_CNTRL) register. This emulates a reduced
frequency Host clock, resulting in associated power savings.
Thermal Throttle Control:
If the THRM# signal is asserted for greater than 2 seconds and the system is not in
a Stop Clock, Sleep, or Deep Sleep state, PIIX4 automatically starts toggling the STPCLK# signal and ZZ signal
(if [ZZ_EN] set) with a period of 244
μ
s and a programmable Duty Cycle. This system toggles between full-
speed operation and the Stop Grant State. The Duty Cycle can be set in 12.5% increments by programming the
[THRM_DTY] bits in the Count B (CNTB) register. The functionality of thermal throttling is independent of
[THRM_EN] bit, which is used to enable events for other power management functions. The [THRM_DTY] field
must be programmed by the BIOS. This emulates a reduced frequency Host clock, resulting in reduced power
and thermal output. When the THRM# signal is negated, the system returns to clock control previously in use.
Stop Break and Burst Execution:
Once the hardware has been placed into a clock control state, it can be
restored to full operation by system hardware or software. Software can restore the system to full operation by
clearing the [CC_EN] bit. Hardware events can be enabled to return the system to a non-clock controlled
condition. If the [BRST_EN] bit is reset, these events are called Stop Break Events. Alternatively, if the
[BRST_EN] bit is set, these events are called Burst Events.
Stop Break events completely return the system to non-clock controlled state. To restore clock control, software
must set the desired clock control configuration and again perform a read from LVL2 or LVL3 registers to initiate
the control.
Burst events cause the reload of a Burst timer, which begins to count down from its loaded value. While the timer
is counting, the system returns to full clock operation. Once the burst timer expires, the system automatically
returns to the clock controlled state. PIIX4 provides two different burst timers, a fast burst timer (which generates
a short count) and a slow burst timer (which generates a longer count).
Care must be taken before placing the system into a LVL2 or LVL3 state when the [BRST_EN] bit is set. Prior to
LVL2 or LVL3 register read, software must ensure that no external burst events are active and only
Device 3 idle timer should be enabled as a burst event. The Device 3 idle timer is then enabled with all reload
events disabled. The LVL2 or LVL3 register read is performed placing the system into a LVL2 or LVL3 clock
control condition. The Device 3 idle timer will then generate a burst event upon expiration. During this first burst,
the desired burst events are then enabled. Failure to follow this procedure may cause the PIIX4 to miss LVL2 or
LVL3 register reads.
The thermal throttle state is not affected by [CC_EN] bit settings, nor are any hardware Stop Break or Burst
events.
Stop Break events are the logical “OR” of Fast Burst and Slow Burst Events. If the [BRST_EN] bit is high, the
Burst events reload their associated burst timer. When the [BRST_EN] bit is low, these events generate
a Stop Break event. The Fast Burst and Slow Burst timer and burst event programming information is
shown on next page.
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PDF描述 |
|---|---|
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| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82371EB | 制造商:Intel 功能描述:IC INTEL 82371EB 352BGA 制造商:Rochester Electronics LLC 功能描述: |
| FW82371EB S L37M | 制造商:Intel 功能描述:Embedded Processor 352-Pin BGA |
| FW82371EB SL37M | 制造商:Intel 功能描述: |
| FW82371MB | 制造商:Rochester Electronics LLC 功能描述:PCI-ISA BRIDGE, T&R, SPEC SL3CG - Bulk |
| FW82439HX | 制造商:Intel 功能描述: |
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