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參數(shù)資料
| 型號(hào)： | FW82371 |
| 廠商： | Intel Corp. |
| 英文描述： | PCI-TO-ISA / IDE XCELERATOR PIIX4 |
| 中文描述： | PCI到的ISA / IDE的XCELERATOR PIIX4 |
| 文件頁(yè)數(shù)： | 21/284頁(yè) |
| 文件大?。?/td> | 1042K |
| 代理商： | FW82371 |
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E
82371AB (PIIX4)
21
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name
Type
Description
SMEMW#
O
STANDARD MEMORY WRITE.
PIIX4 asserts SMEMW# to request an ISA memory
slave to accept data from the data lines. If the access is below the 1-Mbyte range
(00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or ISA master
cycles, PIIX4 asserts SMEMW#. SMEMW# is a delayed version of MEMW#.
During Reset:
High-Z
After Reset:
High
During POS:
High
ZEROWS#
I
ZERO WAIT STATES.
An ISA slave asserts ZEROWS# after its address and
command signals have been decoded to indicate that the current cycle can be
shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An 8-bit
memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect
during 16-bit I/O cycles.
If IOCHRDY is negated and ZEROWS# is asserted during the same clock, then
ZEROWS# is ignored and wait states are added as a function of IOCHRDY.
2.1.3.
X-BUS INTERFACE
Name
Type
Description
A20GATE
I
ADDRESS 20 GATE.
This input from the keyboard controller is logically combined with
bit 1 (FAST_A20) of the Port 92 Register, which is then output via the A20M# signal.
BIOSCS#
O
BIOS CHIP SELECT.
This chip select is driven active during read or write accesses to
enabled BIOS memory ranges. BIOSCS# is driven combinatorially from the ISA
addresses SA[16:0] and LA[23:17], except during DMA cycles.
During DMA cycles,
BIOSCS# is not generated.
During Reset:
High
After Reset:
High
During POS:
High
KBCCS#/
GPO26
O
KEYBOARD CONTROLLER CHIP SELECT.
KBCCS# is asserted during I/O read or
write accesses to KBC locations 60h and 64h. It is driven combinatorially from the ISA
addresses SA[19:0] and LA[23:17].
If the keyboard controller does not require a separate chip select, this signal can be
programmed to a general purpose output.
During Reset:
High
After Reset:
High
During POS:
High/GPO
MCCS#
O
MICROCONTROLLER CHIP SELECT.
MCCS# is asserted during I/O read or write
accesses to IO locations 62h and 66h. It is driven combinatorially from the ISA
addresses SA[19:0] and LA[23:17].
During Reset:
High
After Reset:
High
During POS:
High
PCS0#
PCS1#
O
PROGRAMMABLE CHIP SELECTS.
These active low chip selects are asserted for
ISA I/O cycles which are generated by PCI masters and which hit the programmable
I/O ranges defined in the Power Management section. The X-Bus buffer signals (XOE#
and XDIR#) are enabled while the chip select is active. (i.e., it is assumed that the
peripheral which is selected via this pin resides on the X-Bus.)
During Reset:
High
After Reset:
High
During POS:
High
RCIN#
I
RESET CPU.
This signal from the keyboard controller is used to generate an INIT
signal to the CPU.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW82801E | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| FWB150 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB1510 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB152 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82371EB | 制造商:Intel 功能描述:IC INTEL 82371EB 352BGA 制造商:Rochester Electronics LLC 功能描述: |
| FW82371EB S L37M | 制造商:Intel 功能描述:Embedded Processor 352-Pin BGA |
| FW82371EB SL37M | 制造商:Intel 功能描述: |
| FW82371MB | 制造商:Rochester Electronics LLC 功能描述:PCI-ISA BRIDGE, T&R, SPEC SL3CG - Bulk |
| FW82439HX | 制造商:Intel 功能描述: |
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