E
7.2.7.
82371AB (PIIX4)
141
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
PCNTRL—PROCESSOR CONTROL REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (10h)
00h
Read/Write
Bit
Description
31:18
Reserved.
17
Clock Control Status (CC_STS)—RO.
1=PIIX4 clock control active. 0=PIIX4 clock control inactive.
16:14
Reserved.
13
Clock Run Enable (CLKRUN_EN)—R/W.
1=Enable PCI Clock Run (CLKRUN#) protocol.
0=Disable. When enabled, PIIX4 requests to stop the PCI clock when the PCI bus has been idle for
26 PCI clocks.
12
Stop Clock Enable (STPCLK_EN)—R/W.
1=Enable stopping of Host clock when placed into a
LVL3 clock
control condition.
0=Disable.
11
Sleep Enable (SLEEP_EN)—R/W.
1=Enable assertion of SLP# signal when placed into LVL3 clock
control condition. 0=Disable. This enables Sleep or Deep Sleep clock control for Pentium II
processor.
10
Burst Enable (BST_EN)—R/W.
1=Enable clock control bursting which causes enabled system
events to become Burst events and reload the burst timers. 0=Disable clock control bursting which
causes enabled system events to become Stop Break events and restore the system to normal full-
speed clocked operation.
9
Clock Control Enable (CC_EN)—R/W.
1=Enable clock control. 0=Disable. This enables reads to
the LVL2 and LVL3 registers to cause PIIX4 to enter the enabled clock mode.
8
Reserved.
7:5
Reserved.
4
Throttle Enable (THT_EN)—R/W.
1=Enable system throttle clock control. 0=Disable.
3:1
Throttle Duty Programming Bits (THTL_DTY)—R/W.
Selects the duty cycle of the STPCLK#
signal when the system is in the system throttling mode. The duty cycle indicates the percentage of
time the STPCLK# signal is asserted while in the throttle mode. The field is decoded as follows:
Bits[2:0]
000
001
010
011
Mode
Reserved
12.5%
25%
37.5%
Bits[2:0]
100
101
110
111
Mode
50%
62.5%
75%
87.5%
0
Reserved.